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Searched refs:VMX (Results 1 – 21 of 21) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrTDX.td19 // SEAMCALL - Call to SEAM VMX-root Operation Module
23 // SEAMRET - Return to Legacy VMX-root Operation
H A DX86InstrVMX.td1 //===-- X86InstrVMX.td - VMX Instruction Set Extension -----*- tablegen -*-===//
9 // This file describes the instructions that make up the Intel VMX instruction
15 // VMX instructions
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp918 Register VMX = VMXl; in expandPostRAPseudo() local
920 VMX = VMXu; in expandPostRAPseudo()
928 .addDef(VMX) in expandPostRAPseudo()
934 .addDef(VMX) in expandPostRAPseudo()
942 .addDef(VMX) in expandPostRAPseudo()
945 .addReg(VMX); in expandPostRAPseudo()
951 .addDef(VMX) in expandPostRAPseudo()
954 .addReg(VMX); in expandPostRAPseudo()
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dppc64-i128-abi.ll58 ; VMX (no VSX):
106 ; VMX (no VSX):
133 ; Little Endian (VSX and VMX):
139 ; Big Endian (VSX and VMX)
169 ; Little Endian (VSX and VMX):
177 ; Big Endian (VSX and VMX):
H A Dvec_popcnt.ll2 ; In addition, check the conversions to/from the v2i64 VMX register that was also added in P8.
H A Dvec_add_sub_doubleword.ll5 ; Check VMX 64-bit integer operations
H A Dvec_add_sub_quadword.ll5 ; Check VMX 128-bit integer operations
/llvm-project-15.0.7/lldb/source/Plugins/Process/Linux/
H A DNativeRegisterContextLinux_ppc64le.h92 VMX m_vmx_ppc64le; // VMX registers.
/llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_ppc64le.h16 #define VMX_OFFSET(regname) (offsetof(VMX, regname) + sizeof(GPR) + sizeof(FPR))
18 (offsetof(VSX, regname) + sizeof(GPR) + sizeof(FPR) + sizeof(VMX))
388 } VMX; typedef
H A DRegisterContextFreeBSD_powerpc.cpp169 } VMX; typedef
H A DRegisterInfos_powerpc.h14 #define VMX_OFFSET(regname) (sizeof(GPR) + sizeof(FPR) + offsetof(VMX, regname))
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCScheduleP8.td41 // The Floating-Point Unit (FPU) and Vector Media Extension (VMX) units
45 // In contrast to the P7, the VMX units on P8 are symmetric, so no need to
H A DP10InstrResources.td1758 // 4 Cycles Permute operations, and 7 Cycles VMX Multiply operations, 2 input operands
2037 // 7 Cycles VMX Multiply operations, 2 input operands
2065 // 7 Cycles VMX Multiply operations, 3 input operands
H A DPPCInstrVSX.td15 // ** which VMX and VSX instructions are lane-sensitive and which are not. **
23 // ** When adding new VMX and VSX instructions, please consider whether they **
1961 2. Shift in the VMX register so that the correct doubleword is correctly
1985 // - Now that we set up the shift amount, we shift in the VMX register
2018 // - Now that we set up the shift amount, we shift in the VMX register
2048 // - Now that we set up the shift amount, we shift in the VMX register
2078 // - Now that we set up the shift amount, we shift in the VMX register
2108 - The shift in the VMX register is by 0/8 for opposite element numbers so
2126 - The shift in the VMX register is by 0/8 for opposite element numbers so
2145 - The shift in the VMX register happens for opposite element numbers
[all …]
H A DPPCInstrAltivec.td15 // ** which VMX and VSX instructions are lane-sensitive and which are not. **
23 // ** When adding new VMX and VSX instructions, please consider whether they **
1316 // instructions than VMX instructions)
/llvm-project-15.0.7/libcxxabi/
H A DCMakeLists.txt461 # On AIX, avoid picking up VMX extensions(i.e. vec_malloc) which would change
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZScheduleZ13.td1261 def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VMX(B|F|G|H)?$")>;
H A DSystemZScheduleZ16.td1324 def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VMX(B|F|G|H)?$")>;
H A DSystemZScheduleZ15.td1318 def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VMX(B|F|G|H)?$")>;
H A DSystemZScheduleZ14.td1282 def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VMX(B|F|G|H)?$")>;
H A DSystemZInstrVector.td581 def VMX : BinaryVRRcGeneric<"vmx", 0xE7FF>;