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Searched refs:VMOVRRD (Results 1 – 20 of 20) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dpeephole-phi.mir19 …; CHECK: [[VMOVRRD:%[0-9]+]]:gpr, [[VMOVRRD1:%[0-9]+]]:gpr = VMOVRRD [[DEF]], 14 /* CC::al */, $…
26 ; CHECK: [[PHI:%[0-9]+]]:gpr = PHI [[VMOVRRD]], %bb.1, [[VMOVRS]], %bb.2
33 %1:gpr, %2:gpr = VMOVRRD %0:dpr, 14, $noreg
H A Dsingle-issue-r52.mir29 # CHECK: SU(3): %5:gpr, %6:gpr = VMOVRRD %4:dpr, 14, $noreg
81 %5, %6 = VMOVRRD %4, 14, $noreg
H A Dcortex-a57-misched-vfma.ll71 ; > VMLAfd not-optimized latency to VMOVRRD = 9
148 ; > VMLSfd not-optimized latency to VMOVRRD = 9
H A Dvector-DAGCombine.ll48 ; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
H A Dpredicated-invariant.mir102 ; CHECK: renamable $r0, renamable $r1 = VMOVRRD renamable $d2, 14 /* CC::al */, $noreg
103 …; CHECK: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d3, 14 /* CC::al */, $noreg, i…
152 renamable $r0, renamable $r1 = VMOVRRD renamable $d2, 14 /* CC::al */, $noreg
153 … renamable $r2, renamable $r3 = VMOVRRD killed renamable $d3, 14 /* CC::al */, $noreg, implicit $q1
H A Dlivereg-no-loop-def.mir114 ; CHECK: renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14 /* CC::al */, $noreg
115 …; CHECK: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14 /* CC::al */, $noreg, i…
164 renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14, $noreg
165 renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14, $noreg, implicit $q0
H A Dsubreg-liveness.mir108 ; CHECK: renamable $r0, renamable $r1 = VMOVRRD killed renamable $d0, 14 /* CC::al */, $noreg
157 renamable $r0, renamable $r1 = VMOVRRD killed renamable $d0, 14 /* CC::al */, $noreg
H A Dinvariant-qreg.mir182 ; CHECK: renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14 /* CC::al */, $noreg
183 …; CHECK: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14 /* CC::al */, $noreg, i…
231 renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14 /* CC::al */, $noreg
232 … renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14 /* CC::al */, $noreg, implicit $q0
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp36 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
H A DMLxExpansionPass.cpp189 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
H A DARMInstructionSelector.cpp288 MIB->setDesc(TII.get(ARM::VMOVRRD)); in selectUnmergeValues()
935 BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(ARM::VMOVRRD)) in select()
H A DARMISelLowering.h114 VMOVRRD, // double to two gprs. enumerator
H A DARMISelLowering.cpp1710 MAKE_CASE(ARMISD::VMOVRRD) in getTargetNodeName()
2290 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in PassF64ArgInRegs()
3258 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn()
3327 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) { in isUsedByReturnOnly()
5199 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl, in getCMOV()
5201 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl, in getCMOV()
6237 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, in ExpandBITCAST()
6241 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, in ExpandBITCAST()
14912 if (Op0.getOpcode() == ARMISD::VMOVRRD && in PerformVMOVDRRCombine()
15312 SDValue VMOVRRD = in PerformExtractEltToVMOVRRD() local
[all …]
H A DARMInstrVFP.td27 def arm_fmrrd : SDNode<"ARMISD::VMOVRRD", SDT_VMOVRRD>;
1204 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
2761 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
H A DARMExpandPseudoInsts.cpp1371 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD)) in CMSESaveClearFPRegsV8()
1558 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD)) in CMSERestoreFPRegsV8()
H A DARMScheduleA57.td804 // VMOVRRS/VMOVRRD in common code declared with one WriteFPMOV (instead of 2).
H A DARMFastISel.cpp1995 TII.get(ARM::VMOVRRD), VA.getLocReg()) in ProcessCallArgs()
H A DARMBaseInstrInfo.cpp5465 case ARM::VMOVRRD: in getExtractSubregLikeInputs()
H A DARMISelDAGToDAG.cpp513 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasNoVMLxHazardUse()
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/GlobalISel/
H A Dselect-fp.mir69 ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr, [[UNINTERESTING:%[0-9]+]]:gpr = VMOVRRD [[VREG]]
861 ; CHECK: [[OUT1:%[0-9]+]]:gpr, [[OUT2:%[0-9]+]]:gpr = VMOVRRD %[[DREG]]