Home
last modified time | relevance | path

Searched refs:VMOVDRR (Results 1 – 17 of 17) sorted by relevance

/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/ARM/
H A Dsplit-superreg-piece.mir114 $d1 = VMOVDRR killed $r2, killed $r3, 14, _, implicit-def $q0, debug-location !19
115 …$d0 = VMOVDRR killed $r0, killed $r1, 14, _, implicit killed $q0, implicit-def $q0, debug-location…
H A Dsplit-superreg.mir114 $d1 = VMOVDRR killed $r2, killed $r3, 14, _, implicit-def $q0, debug-location !19
115 …$d0 = VMOVDRR killed $r0, killed $r1, 14, _, implicit killed $q0, implicit-def $q0, debug-location…
H A Dsplit-superreg-complex.mir114 $d1 = VMOVDRR killed $r2, killed $r3, 14, _, implicit-def $q0, debug-location !19
115 …$d0 = VMOVDRR killed $r0, killed $r1, 14, _, implicit killed $q0, implicit-def $q0, debug-location…
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMFixCortexA57AES1742098Pass.cpp163 case ARM::VMOVDRR: in isSafeAESInput()
H A DARMInstrVFP.td26 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
1177 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
1261 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
1293 (VMOVDRR GPR:$Rl, (BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
1296 (VMOVDRR GPR:$Rl, (t2BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
1299 (VMOVDRR GPR:$Rl, (EORri GPR:$Rh, (i32 0x80000000)))>,
1302 (VMOVDRR GPR:$Rl, (t2EORri GPR:$Rh, (i32 0x80000000)))>,
2763 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
H A DARMISelLowering.h115 VMOVDRR, // Two gprs to double. enumerator
H A DARMInstructionSelector.cpp256 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
H A DARM.td260 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
262 // True if VMOVSR will be favored over VMOVDRR.
H A DARMExpandPseudoInsts.cpp1250 BuildMI(ClearBB, DL, TII->get(ARM::VMOVDRR), Reg) in CMSEClearFPRegsV8()
1415 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg) in CMSESaveClearFPRegsV8()
1646 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg) in CMSERestoreFPRegsV8()
H A DARMScheduleSwift.td641 def : InstRW<[SwiftWriteP2FourCycle], (instregex "VMOVDRR$")>;
H A DARMISelLowering.cpp1711 MAKE_CASE(ARMISD::VMOVDRR) in getTargetNodeName()
2206 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
2223 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
5214 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High); in getCMOV()
5988 Tmp0.getOpcode() == ARMISD::VMOVDRR; in LowerFCOPYSIGN()
6059 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerFCOPYSIGN()
7064 return DAG.getNode(ARMISD::VMOVDRR, DL, MVT::f64, Lo, Hi); in LowerConstantFP()
14817 if (InDouble.getOpcode() == ARMISD::VMOVDRR && Subtarget->hasFP64()) in PerformVMOVRRDCombine()
15358 if (MOV.getOpcode() == ARMISD::VMOVDRR) in PerformExtractEltCombine()
16629 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR && in PerformSTORECombine()
[all …]
H A DARMScheduleA57.td808 def : InstRW<[A57Write_8cyc_1L_1I], (instregex "VMOVDRR")>;
H A DARMFastISel.cpp2044 TII.get(ARM::VMOVDRR), ResultReg) in FinishCall()
H A DARMInstrNEON.td6650 // ARMvdup patterns for uarchs with slow VDUP.32 - use VMOVDRR instead.
6651 def : Pat<(v2i32 (ARMvdup (i32 GPR:$R))), (VMOVDRR GPR:$R, GPR:$R)>,
6653 def : Pat<(v2f32 (ARMvdup (f32 (bitconvert GPR:$R)))), (VMOVDRR GPR:$R, GPR:$R)>,
7481 // Prefer VMOVDRR for i32 -> f32 bitcasts, it can write all DPR registers.
7483 (EXTRACT_SUBREG (VMOVDRR GPR:$a, GPR:$a), ssub_0)>,
7486 (EXTRACT_SUBREG (VMOVDRR GPR:$a, GPR:$a), ssub_0)>,
H A DARMBaseInstrInfo.cpp5438 case ARM::VMOVDRR: in getRegSequenceLikeInputs()
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/GlobalISel/
H A Dselect-fp.mir858 ; CHECK: %[[DREG:[0-9]+]]:dpr = VMOVDRR [[IN1]], [[IN2]]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
H A Dvaddv.mir1854 …; CHECK: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $n…
1899 …renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, impli…
2107 …; CHECK: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $n…
2152 …renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, impli…
2360 …; CHECK: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $n…
2405 …renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, impli…
2613 …; CHECK: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $n…
2658 …renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, impli…