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Searched refs:VLMul (Results 1 – 5 of 5) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInsertVSETVLI.cpp288 std::tie(LMul, Fractional) = RISCVVType::decodeVLMUL(VLMul); in getSEWLMULRatio()
420 RISCVII::VLMUL VLMul = RISCVII::LMUL_1; member in __anon1aeaf6f50111::VSETVLIInfo
463 RISCVII::VLMUL getVLMUL() const { return VLMul; } in getVLMUL()
490 VLMul = RISCVVType::getVLMUL(VType); in setVTYPE()
498 VLMul = L; in setVTYPE()
529 return std::tie(VLMul, SEW, TailAgnostic, MaskAgnostic) == in hasSameVTYPE()
530 std::tie(Other.VLMul, Other.SEW, Other.TailAgnostic, in hasSameVTYPE()
537 return ::getSEWLMULRatio(SEW, VLMul); in getSEWLMULRatio()
675 << "VLMul=" << (unsigned)VLMul << ", " in print()
822 RISCVII::VLMUL VLMul = RISCVII::getLMul(TSFlags); in computeInfoForInstr() local
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H A DRISCVInstrInfoVPseudos.td643 let VLMul = m.value;
1240 let VLMul = MInfo.value;
1263 let VLMul = MInfo.value;
1782 let VLMul = m.value in {
1804 let VLMul = m.value in {
1817 let VLMul = m.value in
1943 let VLMul = m.value in {
2100 let VLMul = m.value in {
2134 let VLMul = m.value in {
2147 let VLMul = m.value in {
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H A DRISCVInstrFormats.td177 bits<3> VLMul = 0;
178 let TSFlags{10-8} = VLMul;
H A DRISCVRegisterInfo.td487 int VLMul = Vlmul;
H A DRISCVISelDAGToDAG.cpp542 RISCVII::VLMUL VLMul = static_cast<RISCVII::VLMUL>( in selectVSETVLI() local
545 unsigned VTypeI = RISCVVType::encodeVTYPE(VLMul, SEW, /*TailAgnostic*/ true, in selectVSETVLI()