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Searched refs:VGPR0 (Results 1 – 14 of 14) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dllvm.amdgcn.mov.dpp8.ll17 ; GFX10PLUS: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s{{[0-9]+}}
18 ; GFX10PLUS: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] dpp8:[1,0,0,0,0,0,0,0]{{$}}
19 ; GFX10PLUS: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] dpp8:[5,0,0,0,0,0,0,0]{{$}}
H A Dllvm.amdgcn.mov.dpp.ll22 ; VI: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s{{[0-9]+}}
24 ; VI-OPT: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_c…
25 ; VI-NOOPT: v_mov_b32_dpp [[VGPR1]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound…
27 ; VI-OPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound…
40 ; VI: v_mov_b32_dpp [[VGPR0:v[0-9]+]], v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 b…
43 ; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou…
H A Duse-sgpr-multiple-times.ll155 ; GCN-DAG: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s[[SGPR0]]
158 ; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[SK]], [[SK]], [[VGPR0]]
185 ; GCN-DAG: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s[[SGPR0]]
188 ; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[VGPR0]], [[SK]], [[SK]]
215 ; GCN-DAG: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s[[SGPR0]]
218 ; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[VGPR0]], [[SK]], [[SK]]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSILateBranchLowering.cpp91 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
92 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
93 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
94 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
H A DAMDGPUCallingConv.td33 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
47 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
80 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
113 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
187 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
199 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
H A DGCNNSAReassign.cpp148 unsigned MaxReg = MaxNumVGPRs - NumRegs + AMDGPU::VGPR0; in scavengeRegs()
150 for (unsigned Reg = AMDGPU::VGPR0; Reg <= MaxReg; ++Reg) { in scavengeRegs()
H A DSIInsertWaitcnts.cpp84 unsigned VGPR0; member
480 assert(Reg >= Encoding.VGPR0 && Reg <= Encoding.VGPRL); in getRegInterval()
481 Result.first = Reg - Encoding.VGPR0; in getRegInterval()
1789 Encoding.VGPR0 = TRI->getEncodingValue(AMDGPU::VGPR0); in runOnMachineFunction()
1790 Encoding.VGPRL = Encoding.VGPR0 + NumVGPRsMax - 1; in runOnMachineFunction()
H A DAMDGPUCallLowering.cpp673 CCInfo.AllocateReg(AMDGPU::VGPR0); in lowerFormalArguments()
H A DSOPInstructions.td840 // VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
H A DSIRegisterInfo.cpp183 TmpVGPR = AMDGPU::VGPR0; in prepare()
H A DSIISelLowering.cpp1885 Register Reg = AMDGPU::VGPR0; in allocateSpecialEntryInputVGPRs()
1897 Info.setWorkItemIDY(ArgDescriptor::createRegister(AMDGPU::VGPR0, in allocateSpecialEntryInputVGPRs()
1911 Info.setWorkItemIDZ(ArgDescriptor::createRegister(AMDGPU::VGPR0, in allocateSpecialEntryInputVGPRs()
2396 CCInfo.AllocateReg(AMDGPU::VGPR0); in LowerFormalArguments()
/llvm-project-15.0.7/llvm/docs/
H A DAMDGPUUsage.rst1852 1536-1791 VGPR0-VGPR255 32*32 Vector General Purpose Registers
1864 2560-2815 VGPR0-VGPR255 64*32 Vector General Purpose Registers
4698 for enabled registers are dense starting at VGPR0: the first enabled register is
4699 VGPR0, the next enabled register is VGPR1 etc.; disabled registers do not have a
4709 specifies *Packed work-item IDs*, the initial value of VGPR0 register is used
13294 ``VGPR0``:
13473 6. VGPR0-31 and SGPR4-29 are used to pass function input arguments as described
13521 1. VGPR0-31 and SGPR4-29 are used to pass function result arguments as
13708 * VGPR arguments are assigned to consecutive VGPRs starting at VGPR0 up to
/llvm-project-15.0.7/llvm/docs/AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack/
H A DAMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack.md560 DW_OP_regx VGPR0
614 DW_OP_regx VGPR0
629 The DW_OP_regx VGPR0 pushes a location description for the first register.
697 DW_OP_regx VGPR0
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp4357 if (VGPR32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1)) in validateVGPRAlign()
4425 auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0); in validateGWS()