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/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dif-pred-stores.ll111 ; VEC-LABEL: @test(
112 ; VEC-NEXT: entry:
147 ; VEC: for.body:
153 ; VEC: if.then:
157 ; VEC: for.inc:
161 ; VEC: for.end:
346 ; VEC-NEXT: entry:
562 ; VEC-NEXT: entry:
606 ; VEC: if.then:
611 ; VEC: for.inc:
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dsincospi.ll22 ; CHECK-FLOAT-IN-VEC-LABEL: @test_instbased_f32(
29 ; CHECK-FLOAT-IN-VEC-NEXT: [[RES:%.*]] = fadd float [[SINPI]], [[COSPI]]
30 ; CHECK-FLOAT-IN-VEC-NEXT: ret float [[RES]]
59 ; CHECK-FLOAT-IN-VEC-LABEL: @test_constant_f32(
66 ; CHECK-FLOAT-IN-VEC-NEXT: ret float [[RES]]
92 ; CHECK-FLOAT-IN-VEC-LABEL: @test_instbased_f64(
100 ; CHECK-FLOAT-IN-VEC-NEXT: ret double [[RES]]
129 ; CHECK-FLOAT-IN-VEC-LABEL: @test_constant_f64(
136 ; CHECK-FLOAT-IN-VEC-NEXT: ret double [[RES]]
162 ; CHECK-FLOAT-IN-VEC-LABEL: @test_fptr(
[all …]
H A Dcanonicalize-vector-extract.ll21 ; CHECK-NEXT: ret <8 x i32> [[VEC:%.*]]
33 ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <2 x i32> <i…
42 ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <2 x i32> <i…
51 ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <2 x i32> <i…
60 ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <2 x i32> <i…
69 ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <4 x i32> <i…
78 ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <4 x i32> <i…
87 ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <3 x i32> <i…
96 ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> poison, <3 x i32> <i…
111 …P1:%.*]] = call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> [[VEC:%.*]], i64 0)
H A Dvscale_extractelement-inseltpoison.ll64 ; CHECK-NEXT: [[VEC:%.*]] = insertelement <vscale x 2 x i32> [[A:%.*]], i32 [[X:%.*]], i64 1
65 ; CHECK-NEXT: call void @use_vscale_2_i32(<vscale x 2 x i32> [[VEC]])
66 ; CHECK-NEXT: [[VEC_CAST:%.*]] = bitcast <vscale x 2 x i32> [[VEC]] to <vscale x 8 x i8>
79 ; CHECK-NEXT: [[VEC:%.*]] = insertelement <vscale x 2 x i32> [[A:%.*]], i32 [[X:%.*]], i64 1
80 ; CHECK-NEXT: [[VEC_CAST:%.*]] = bitcast <vscale x 2 x i32> [[VEC]] to <vscale x 8 x i8>
120 ; CHECK-NEXT: ret <vscale x 4 x i32> [[VEC:%.*]]
135 ; CHECK-NEXT: [[VEC_E0:%.*]] = extractelement <vscale x 4 x i32> [[VEC:%.*]], i64 4
136 ; CHECK-NEXT: [[VEC_E1:%.*]] = extractelement <vscale x 4 x i32> [[VEC]], i64 5
137 ; CHECK-NEXT: [[VEC_E2:%.*]] = extractelement <vscale x 4 x i32> [[VEC]], i64 6
138 ; CHECK-NEXT: [[VEC_E3:%.*]] = extractelement <vscale x 4 x i32> [[VEC]], i64 7
[all …]
H A Dcanonicalize-vector-insert.ll34 ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[VEC:%.*]], <8 x i32> …
44 ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> [[TMP1]], <8 x i32> …
54 ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> [[TMP1]], <8 x i32> …
64 ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> [[TMP1]], <8 x i32> …
74 ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[VEC:%.*]], <8 x i32> …
84 ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> [[TMP1]], <8 x i32> …
94 ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[VEC:%.*]], <8 x i32> …
104 ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> [[TMP1]], <8 x i32> …
119 … <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> [[VEC:%.*]], <4 x i32> [[…
H A Dicmp-bc-vec.ll77 ; CHECK-NEXT: [[VEC:%.*]] = shufflevector <4 x i8> [[INVEC:%.*]], <4 x i8> undef, <4 x i32> <i32…
78 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i8> [[VEC]] to i32
92 ; CHECK-NEXT: [[VEC:%.*]] = shufflevector <4 x i8> [[INSVEC]], <4 x i8> undef, <4 x i32> zeroini…
93 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i8> [[VEC]] to i32
H A Dicmp-bc-vec-inseltpoison.ll77 ; CHECK-NEXT: [[VEC:%.*]] = shufflevector <4 x i8> [[INVEC:%.*]], <4 x i8> poison, <4 x i32> <i3…
78 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i8> [[VEC]] to i32
92 ; CHECK-NEXT: [[VEC:%.*]] = shufflevector <4 x i8> [[INSVEC]], <4 x i8> poison, <4 x i32> zeroin…
93 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i8> [[VEC]] to i32
/llvm-project-15.0.7/llvm/test/CodeGen/Generic/
H A Dexpand-experimental-reductions.ll27 ; CHECK-NEXT: [[BIN_RDX:%.*]] = add <2 x i64> [[VEC]], [[RDX_SHUF]]
40 ; CHECK-NEXT: [[BIN_RDX:%.*]] = mul <2 x i64> [[VEC]], [[RDX_SHUF]]
53 ; CHECK-NEXT: [[BIN_RDX:%.*]] = and <2 x i64> [[VEC]], [[RDX_SHUF]]
66 ; CHECK-NEXT: [[BIN_RDX:%.*]] = or <2 x i64> [[VEC]], [[RDX_SHUF]]
79 ; CHECK-NEXT: [[BIN_RDX:%.*]] = xor <2 x i64> [[VEC]], [[RDX_SHUF]]
125 ; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[VEC]], i32 1
127 ; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[VEC]], i32 2
129 ; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[VEC]], i32 3
143 ; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[VEC]], i32 1
145 ; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[VEC]], i32 2
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dvec-args-01.ll3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
16 ; CHECK-VEC-LABEL: foo:
17 ; CHECK-VEC-DAG: vrepif %v24, 1
18 ; CHECK-VEC-DAG: vrepif %v26, 2
19 ; CHECK-VEC-DAG: vrepif %v28, 3
20 ; CHECK-VEC-DAG: vrepif %v30, 4
21 ; CHECK-VEC-DAG: vrepif %v25, 5
22 ; CHECK-VEC-DAG: vrepif %v27, 6
23 ; CHECK-VEC-DAG: vrepif %v29, 7
24 ; CHECK-VEC-DAG: vrepif %v31, 8
[all …]
H A Dvec-args-04.ll3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
13 ; CHECK-VEC-LABEL: foo:
14 ; CHECK-VEC-DAG: vrepib %v24, 1
15 ; CHECK-VEC-DAG: vrepib %v26, 2
16 ; CHECK-VEC-DAG: vrepib %v28, 3
17 ; CHECK-VEC-DAG: vrepib %v30, 4
18 ; CHECK-VEC-DAG: vrepib %v25, 5
19 ; CHECK-VEC-DAG: vrepib %v27, 6
20 ; CHECK-VEC-DAG: vrepib %v29, 7
21 ; CHECK-VEC-DAG: vrepib %v31, 8
[all …]
H A Dvec-args-02.ll3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
12 ; CHECK-VEC-LABEL: foo:
13 ; CHECK-VEC-DAG: vrepif %v24, 1
14 ; CHECK-VEC-DAG: vrepif %v26, 2
15 ; CHECK-VEC: brasl %r14, bar@PLT
H A Dvec-args-05.ll3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
12 ; CHECK-VEC-LABEL: foo:
13 ; CHECK-VEC-DAG: vrepib %v24, 1
14 ; CHECK-VEC-DAG: vrepib %v26, 2
15 ; CHECK-VEC: brasl %r14, bar@PLT
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/
H A Darbitrary-induction-step.ll23 ; FORCE-VEC-LABEL: @ind_plus2(
25 ; FORCE-VEC: mul nsw <2 x i32>
26 ; FORCE-VEC: add <2 x i32>
28 ; FORCE-VEC: icmp eq i64 %index.next, 512
67 ; FORCE-VEC-LABEL: @ind_minus2(
69 ; FORCE-VEC: mul nsw <2 x i32>
70 ; FORCE-VEC: add <2 x i32>
118 ; FORCE-VEC-LABEL: @ptr_ind_plus2(
119 ; FORCE-VEC: %[[V:.*]] = load <4 x i32>
122 ; FORCE-VEC: mul nsw <2 x i32>
[all …]
/llvm-project-15.0.7/mlir/test/Conversion/GPUToSPIRV/
H A Dbuiltins.mlir17 // CHECK-NEXT: [[VEC:%.*]] = spv.Load "Input" [[ADDRESS]]
43 // CHECK-NEXT: [[VEC:%.*]] = spv.Load "Input" [[ADDRESS]]
67 // CHECK-NEXT: [[VEC:%.*]] = spv.Load "Input" [[ADDRESS]]
160 // CHECK-NEXT: [[VEC:%.*]] = spv.Load "Input" [[ADDRESS]]
184 // CHECK-NEXT: [[VEC:%.*]] = spv.Load "Input" [[ADDRESS]]
240 // CHECK-NEXT: [[VEC:%.*]] = spv.Load "Input" [[ADDRESS]]
264 // CHECK-NEXT: [[VEC:%.*]] = spv.Load "Input" [[ADDRESS]]
288 // CHECK-NEXT: [[VEC:%.*]] = spv.Load "Input" [[ADDRESS]]
312 // CHECK-NEXT: [[VEC:%.*]] = spv.Load "Input" [[ADDRESS]]
336 // CHECK-NEXT: [[VEC:%.*]] = spv.Load "Input" [[ADDRESS]]
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/ValueTracking/
H A Dsignbits-extract-elt.ll20 ; CHECK-NEXT: [[VEC:%.*]] = sext <2 x i1> [[VEC:%.*]]in to <2 x i32>
21 ; CHECK-NEXT: [[ELT0:%.*]] = extractelement <2 x i32> [[VEC]], i32 0
/llvm-project-15.0.7/llvm/test/Transforms/RewriteStatepointsForGC/
H A Dbase-vector.ll11 ; CHECK-NEXT: [[OBJ:%.*]] = extractelement <2 x i64 addrspace(1)*> [[VEC:%.*]], i32 [[IDX:%.*]]
37 ; CHECK-NEXT: [[OBJ0:%.*]] = extractelement <2 x i64 addrspace(1)*> [[VEC]], i32 [[IDX1:%.*]]
40 ; CHECK-NEXT: [[OBJ1:%.*]] = extractelement <2 x i64 addrspace(1)*> [[VEC]], i32 [[IDX2:%.*]]
84 ; CHECK-NEXT: [[OBJ:%.*]] = extractelement <2 x i64 addrspace(1)*> [[VEC]], i32 0
110 ; CHECK-NEXT: [[OBJ:%.*]] = extractelement <2 x i64 addrspace(1)*> [[VEC]], i32 0
138 ; CHECK-NEXT: [[BDV:%.*]] = extractelement <2 x i64 addrspace(1)*> [[VEC]], i32 0
166 ; CHECK-NEXT: [[BDV:%.*]] = extractelement <2 x i64 addrspace(1)*> [[VEC]], i64 [[IDX]]
249 ; CHECK-NEXT: [[BDV:%.*]] = extractelement <2 x i64 addrspace(1)*> [[VEC]], i64 [[IDX]]
276 ; CHECK-NEXT: [[BDV:%.*]] = extractelement <2 x i64 addrspace(1)*> [[VEC]], i64 [[IDX:%.*]]
307 …XT: [[VEC3]] = shufflevector <4 x i64 addrspace(1)*> [[VEC]], <4 x i64 addrspace(1)*> [[VEC]], …
[all …]
H A Dbase-vector-inseltpoison.ll9 ; CHECK-NEXT: [[OBJ:%.*]] = extractelement <2 x i64 addrspace(1)*> [[VEC:%.*]], i32 [[IDX:%.*]]
37 ; CHECK-NEXT: [[OBJ0:%.*]] = extractelement <2 x i64 addrspace(1)*> [[VEC]], i32 [[IDX1:%.*]]
40 ; CHECK-NEXT: [[OBJ1:%.*]] = extractelement <2 x i64 addrspace(1)*> [[VEC]], i32 [[IDX2:%.*]]
84 ; CHECK-NEXT: [[OBJ:%.*]] = extractelement <2 x i64 addrspace(1)*> [[VEC]], i32 0
108 ; CHECK-NEXT: [[OBJ:%.*]] = extractelement <2 x i64 addrspace(1)*> [[VEC]], i32 0
137 ; CHECK-NEXT: [[BDV:%.*]] = extractelement <2 x i64 addrspace(1)*> [[VEC]], i32 0
163 ; CHECK-NEXT: [[BDV:%.*]] = extractelement <2 x i64 addrspace(1)*> [[VEC]], i64 [[IDX]]
249 ; CHECK-NEXT: [[BDV:%.*]] = extractelement <2 x i64 addrspace(1)*> [[VEC]], i64 [[IDX]]
276 ; CHECK-NEXT: [[BDV:%.*]] = extractelement <2 x i64 addrspace(1)*> [[VEC]], i64 [[IDX:%.*]]
307 …XT: [[VEC3]] = shufflevector <4 x i64 addrspace(1)*> [[VEC]], <4 x i64 addrspace(1)*> [[VEC]], …
[all …]
H A Dscalar-base-vector.ll24 ; CHECK-NEXT: [[VEC:%.*]] = getelementptr i32, <2 x i32 addrspace(1)*> [[DOTSPLAT]], <2 x i64> […
26 ; CHECK-NEXT: [[PTR:%.*]] = extractelement <2 x i32 addrspace(1)*> [[VEC]], i32 1
59 ; CHECK-NEXT: [[VEC:%.*]] = getelementptr i32, <2 x i32 addrspace(1)*> [[DOTSPLAT]], <2 x i64> […
61 ; CHECK-NEXT: [[PTR:%.*]] = extractelement <2 x i32 addrspace(1)*> [[VEC]], i32 1
81 ; CHECK-NEXT: [[VEC:%.*]] = getelementptr i32, <2 x i32 addrspace(1)*> [[BASE_I32]], <2 x i64> […
83 ; CHECK-NEXT: [[PTR:%.*]] = extractelement <2 x i32 addrspace(1)*> [[VEC]], i32 1
107 ; CHECK-NEXT: [[VEC:%.*]] = getelementptr i32, <2 x i32 addrspace(1)*> [[DOTSPLAT]], <2 x i64> […
108 …fepoint, i32 0, i32 0, i32 0, i32 0) [ "gc-live"(<2 x i32 addrspace(1)*> [[VEC]], <2 x i32 addrspa…
128 ; CHECK-NEXT: [[VEC:%.*]] = getelementptr i32, <2 x i32 addrspace(1)*> [[BASE_I32]], <2 x i64> […
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dextract_vector_elt-f16.ll5 ; GCN: s_load_dword [[VEC:s[0-9]+]]
6 ; GCN: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], 16
7 ; GCN-DAG: v_mov_b32_e32 [[VELT0:v[0-9]+]], [[VEC]]
23 ; GCN: s_load_dword [[VEC:s[0-9]+]]
25 ; GCN: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], [[IDX_SCALED]]
37 ; GCN-DAG: s_load_dword [[VEC:s[0-9]+]]
41 ; SI: v_lshr_b32_e32 [[ELT:v[0-9]+]], [[VEC]], [[IDX_SCALED]]
42 ; VI: v_lshrrev_b32_e64 [[ELT:v[0-9]+]], [[IDX_SCALED]], [[VEC]]
H A Dextract_vector_elt-i16.ll6 ; GCN: s_load_dword [[VEC:s[0-9]+]]
7 ; SIVI: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], 16
8 ; SIVI-DAG: v_mov_b32_e32 [[VELT0:v[0-9]+]], [[VEC]]
12 ; GFX9: v_mov_b32_e32 [[VVEC:v[0-9]+]], [[VEC]]
27 ; GCN: s_load_dword [[VEC:s[0-9]+]]
29 ; GCN: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], [[IDX_SCALED]]
43 ; GCN-DAG: s_load_dword [[VEC:s[0-9]+]]
45 ; SI: v_lshr_b32_e32 [[ELT:v[0-9]+]], [[VEC]], [[IDX_SCALED]]
46 ; VI: v_lshrrev_b32_e64 [[ELT:v[0-9]+]], [[IDX_SCALED]], [[VEC]]
/llvm-project-15.0.7/llvm/test/Transforms/VectorCombine/AArch64/
H A Dextract-scalable.ll28 ; CHECK-NEXT: [[ELT0:%.*]] = extractelement <vscale x 4 x i32> [[VEC:%.*]], i32 0
29 ; CHECK-NEXT: [[ELT1:%.*]] = extractelement <vscale x 4 x i32> [[VEC]], i32 1
31 ; CHECK-NEXT: [[ELTIDX:%.*]] = extractelement <vscale x 4 x i32> [[VEC]], i32 [[IDX]]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/AArch64/
H A Dtbl1.ll15 ; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <16 x i8> [[VEC:%.*]], <16 x i8> poison, <8 x i32> <i…
27 ; CHECK-NEXT: [[TBL1:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> [[VEC:%.*]], <…
39 ; CHECK-NEXT: [[TBL1:%.*]] = call <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8> [[VEC:%.*]],…
51 ; CHECK-NEXT: [[TBL1:%.*]] = call <8 x i16> @llvm.aarch64.neon.tbl1.v8i16(<16 x i8> [[VEC:%.*]],…
/llvm-project-15.0.7/mlir/test/Dialect/Vector/
H A Dvector-transfer-flatten.mlir31 // C-HECK-SAME: %[[VEC:[0-9a-zA-Z]+]]: vector<5x4x3x2xi8>
33 // C-HECK-DAG: %[[VEC1D:.+]] = vector.shape_cast %[[VEC]] : vector<5x4x3x2xi8> to vector<120xi8>
45 // CHECK-SAME: %[[VEC:.+]]: vector<i8>
46 // CHECK: vector.transfer_write %[[VEC]], %[[ARG]][] : vector<i8>, memref<i8>
/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/AArch64/
H A Dpeel-multiple-unreachable-exits-for-vectorization.ll13 ; CHECK-NEXT: [[GEP_START_I:%.*]] = getelementptr [[VEC:%.*]], %vec* [[A:%.*]], i64 0, i32 0
15 ; CHECK-NEXT: [[GEP_END_I:%.*]] = getelementptr [[VEC]], %vec* [[A]], i64 0, i32 1
20 ; CHECK-NEXT: [[GEP_END_I3:%.*]] = getelementptr [[VEC]], %vec* [[B:%.*]], i64 0, i32 1
21 ; CHECK-NEXT: [[GEP_START_I1:%.*]] = getelementptr [[VEC]], %vec* [[B]], i64 0, i32 0
129 ; CHECK-NEXT: [[GEP_START_I:%.*]] = getelementptr [[VEC:%.*]], %vec* [[A:%.*]], i64 0, i32 0
131 ; CHECK-NEXT: [[GEP_END_I:%.*]] = getelementptr [[VEC]], %vec* [[A]], i64 0, i32 1
136 ; CHECK-NEXT: [[GEP_START_I13:%.*]] = getelementptr [[VEC]], %vec* [[C:%.*]], i64 0, i32 0
137 ; CHECK-NEXT: [[GEP_END_I15:%.*]] = getelementptr [[VEC]], %vec* [[C]], i64 0, i32 1
138 ; CHECK-NEXT: [[GEP_END_I3:%.*]] = getelementptr [[VEC]], %vec* [[B:%.*]], i64 0, i32 1
139 ; CHECK-NEXT: [[GEP_START_I1:%.*]] = getelementptr [[VEC]], %vec* [[B]], i64 0, i32 0
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/X86/
H A Dx86-amx-load-store.ll8 ; CHECK-NEXT: [[VEC:%.*]] = load <256 x i32>, <256 x i32>* [[SRC:%.*]], align 64
9 ; CHECK-NEXT: [[BC:%.*]] = bitcast <256 x i32> [[VEC]] to x86_amx

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