Lines Matching refs:VEC
4 …nfo -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s --check-prefix=VEC
111 ; VEC-LABEL: @test(
112 ; VEC-NEXT: entry:
113 ; VEC-NEXT: br label [[VECTOR_BODY:%.*]]
114 ; VEC: vector.body:
115 ; VEC-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CON…
116 ; VEC-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
117 ; VEC-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, i32* [[F:%.*]], i64 [[TMP0]]
118 ; VEC-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 0
119 ; VEC-NEXT: [[TMP3:%.*]] = bitcast i32* [[TMP2]] to <2 x i32>*
120 ; VEC-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, <2 x i32>* [[TMP3]], align 4
121 ; VEC-NEXT: [[TMP4:%.*]] = icmp sgt <2 x i32> [[WIDE_LOAD]], <i32 100, i32 100>
122 ; VEC-NEXT: [[TMP5:%.*]] = extractelement <2 x i1> [[TMP4]], i32 0
123 ; VEC-NEXT: br i1 [[TMP5]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
124 ; VEC: pred.store.if:
125 ; VEC-NEXT: [[TMP6:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i32 0
126 ; VEC-NEXT: [[TMP7:%.*]] = add nsw i32 [[TMP6]], 20
127 ; VEC-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, i32* [[F]], i64 [[TMP0]]
128 ; VEC-NEXT: store i32 [[TMP7]], i32* [[TMP8]], align 4
129 ; VEC-NEXT: br label [[PRED_STORE_CONTINUE]]
130 ; VEC: pred.store.continue:
131 ; VEC-NEXT: [[TMP9:%.*]] = extractelement <2 x i1> [[TMP4]], i32 1
132 ; VEC-NEXT: br i1 [[TMP9]], label [[PRED_STORE_IF1:%.*]], label [[PRED_STORE_CONTINUE2]]
133 ; VEC: pred.store.if1:
134 ; VEC-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 1
135 ; VEC-NEXT: [[TMP11:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i32 1
136 ; VEC-NEXT: [[TMP12:%.*]] = add nsw i32 [[TMP11]], 20
137 ; VEC-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, i32* [[F]], i64 [[TMP10]]
138 ; VEC-NEXT: store i32 [[TMP12]], i32* [[TMP13]], align 4
139 ; VEC-NEXT: br label [[PRED_STORE_CONTINUE2]]
140 ; VEC: pred.store.continue2:
141 ; VEC-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
142 ; VEC-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128
143 ; VEC-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOO…
144 ; VEC: middle.block:
145 ; VEC-NEXT: [[CMP_N:%.*]] = icmp eq i64 128, 128
146 ; VEC-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[FOR_BODY:%.*]]
147 ; VEC: for.body:
148 ; VEC-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_INC:%.*]] ], [ 128, [[…
149 ; VEC-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[F]], i64 [[INDVARS_IV]]
150 ; VEC-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
151 ; VEC-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP15]], 100
152 ; VEC-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[FOR_INC]]
153 ; VEC: if.then:
154 ; VEC-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 20
155 ; VEC-NEXT: store i32 [[ADD]], i32* [[ARRAYIDX]], align 4
156 ; VEC-NEXT: br label [[FOR_INC]]
157 ; VEC: for.inc:
158 ; VEC-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
159 ; VEC-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 128
160 ; VEC-NEXT: br i1 [[EXITCOND]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]…
161 ; VEC: for.end:
162 ; VEC-NEXT: ret i32 0
345 ; VEC-LABEL: @bug18724(
346 ; VEC-NEXT: entry:
347 ; VEC-NEXT: [[TMP0:%.*]] = xor i1 [[COND:%.*]], true
348 ; VEC-NEXT: call void @llvm.assume(i1 [[TMP0]])
349 ; VEC-NEXT: [[TMP1:%.*]] = trunc i64 [[V_1:%.*]] to i32
350 ; VEC-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP1]], i32 0)
351 ; VEC-NEXT: [[TMP2:%.*]] = sub i32 [[SMAX]], [[TMP1]]
352 ; VEC-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
353 ; VEC-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP3]], 1
354 ; VEC-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP4]], 2
355 ; VEC-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
356 ; VEC: vector.ph:
357 ; VEC-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP4]], 2
358 ; VEC-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP4]], [[N_MOD_VF]]
359 ; VEC-NEXT: [[IND_END:%.*]] = add i64 [[V_1]], [[N_VEC]]
360 ; VEC-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> zeroinitializer, i32 [[V_2:%.*]], i32 0
361 ; VEC-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i1> poison, i1 [[COND_2:%.*]], i3…
362 ; VEC-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i1> [[BROADCAST_SPLATINSERT]], <2 x i1>…
363 ; VEC-NEXT: br label [[VECTOR_BODY:%.*]]
364 ; VEC: vector.body:
365 ; VEC-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CON…
366 ; VEC-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ [[TMP5]], [[VECTOR_PH]] ], [ [[PREDPHI:%.*]], [[PR…
367 ; VEC-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[V_1]], [[INDEX]]
368 ; VEC-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 0
369 ; VEC-NEXT: [[TMP7:%.*]] = getelementptr inbounds [768 x i32], [768 x i32]* [[PTR:%.*]], i64 0, …
370 ; VEC-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, i32* [[TMP7]], i32 0
371 ; VEC-NEXT: [[TMP9:%.*]] = bitcast i32* [[TMP8]] to <2 x i32>*
372 ; VEC-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, <2 x i32>* [[TMP9]], align 4
373 ; VEC-NEXT: [[TMP10:%.*]] = extractelement <2 x i1> [[BROADCAST_SPLAT]], i32 0
374 ; VEC-NEXT: br i1 [[TMP10]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
375 ; VEC: pred.store.if:
376 ; VEC-NEXT: [[TMP11:%.*]] = getelementptr inbounds [768 x i32], [768 x i32]* [[PTR]], i64 0, i64…
377 ; VEC-NEXT: [[TMP12:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i32 0
378 ; VEC-NEXT: store i32 [[TMP12]], i32* [[TMP11]], align 4
379 ; VEC-NEXT: br label [[PRED_STORE_CONTINUE]]
380 ; VEC: pred.store.continue:
381 ; VEC-NEXT: [[TMP13:%.*]] = extractelement <2 x i1> [[BROADCAST_SPLAT]], i32 1
382 ; VEC-NEXT: br i1 [[TMP13]], label [[PRED_STORE_IF1:%.*]], label [[PRED_STORE_CONTINUE2]]
383 ; VEC: pred.store.if1:
384 ; VEC-NEXT: [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], 1
385 ; VEC-NEXT: [[TMP15:%.*]] = getelementptr inbounds [768 x i32], [768 x i32]* [[PTR]], i64 0, i64…
386 ; VEC-NEXT: [[TMP16:%.*]] = extractelement <2 x i32> [[WIDE_LOAD]], i32 1
387 ; VEC-NEXT: store i32 [[TMP16]], i32* [[TMP15]], align 4
388 ; VEC-NEXT: br label [[PRED_STORE_CONTINUE2]]
389 ; VEC: pred.store.continue2:
390 ; VEC-NEXT: [[TMP17:%.*]] = add <2 x i32> [[VEC_PHI]], <i32 1, i32 1>
391 ; VEC-NEXT: [[TMP18:%.*]] = xor <2 x i1> [[BROADCAST_SPLAT]], <i1 true, i1 true>
392 ; VEC-NEXT: [[PREDPHI]] = select <2 x i1> [[TMP18]], <2 x i32> [[VEC_PHI]], <2 x i32> [[TMP17]]
393 ; VEC-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
394 ; VEC-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
395 ; VEC-NEXT: br i1 [[TMP19]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOO…
396 ; VEC: middle.block:
397 ; VEC-NEXT: [[TMP20:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[PREDPHI]])
398 ; VEC-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP4]], [[N_VEC]]
399 ; VEC-NEXT: [[TMP21:%.*]] = xor i1 [[CMP_N]], true
400 ; VEC-NEXT: call void @llvm.assume(i1 [[TMP21]])
401 ; VEC-NEXT: br label [[SCALAR_PH]]
402 ; VEC: scalar.ph:
403 ; VEC-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[V_1]], [[ENTR…
404 ; VEC-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[V_2]], [[ENTRY]] ], [ [[TMP20]], [[MIDDLE_BLOCK]]…
405 ; VEC-NEXT: br label [[FOR_BODY14:%.*]]
406 ; VEC: for.body14:
407 ; VEC-NEXT: [[INDVARS_IV3:%.*]] = phi i64 [ [[INDVARS_IV_NEXT4:%.*]], [[FOR_INC23:%.*]] ], [ [[B…
408 ; VEC-NEXT: [[INEWCHUNKS_120:%.*]] = phi i32 [ [[INEWCHUNKS_2:%.*]], [[FOR_INC23]] ], [ [[BC_MER…
409 ; VEC-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [768 x i32], [768 x i32]* [[PTR]], i64 0…
410 ; VEC-NEXT: [[TMP:%.*]] = load i32, i32* [[ARRAYIDX16]], align 4
411 ; VEC-NEXT: br i1 [[COND_2]], label [[IF_THEN18:%.*]], label [[FOR_INC23]]
412 ; VEC: if.then18:
413 ; VEC-NEXT: store i32 [[TMP]], i32* [[ARRAYIDX16]], align 4
414 ; VEC-NEXT: [[INC21:%.*]] = add nsw i32 [[INEWCHUNKS_120]], 1
415 ; VEC-NEXT: br label [[FOR_INC23]]
416 ; VEC: for.inc23:
417 ; VEC-NEXT: [[INEWCHUNKS_2]] = phi i32 [ [[INC21]], [[IF_THEN18]] ], [ [[INEWCHUNKS_120]], [[FOR…
418 ; VEC-NEXT: [[INDVARS_IV_NEXT4]] = add nsw i64 [[INDVARS_IV3]], 1
419 ; VEC-NEXT: [[TMP1:%.*]] = trunc i64 [[INDVARS_IV3]] to i32
420 ; VEC-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP1]], 0
421 ; VEC-NEXT: call void @llvm.assume(i1 [[CMP13]])
422 ; VEC-NEXT: br label [[FOR_BODY14]]
561 ; VEC-LABEL: @minimal_bit_widths(
562 ; VEC-NEXT: entry:
563 ; VEC-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i1> poison, i1 [[C:%.*]], i32 0
564 ; VEC-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i1> [[BROADCAST_SPLATINSERT]], <2 x i1>…
565 ; VEC-NEXT: br label [[VECTOR_BODY:%.*]]
566 ; VEC: vector.body:
567 ; VEC-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CON…
568 ; VEC-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
569 ; VEC-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* undef, i64 [[TMP0]]
570 ; VEC-NEXT: [[TMP3:%.*]] = getelementptr i8, i8* [[TMP2]], i32 0
571 ; VEC-NEXT: [[TMP4:%.*]] = bitcast i8* [[TMP3]] to <2 x i8>*
572 ; VEC-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i8>, <2 x i8>* [[TMP4]], align 1
573 ; VEC-NEXT: [[TMP5:%.*]] = extractelement <2 x i1> [[BROADCAST_SPLAT]], i32 0
574 ; VEC-NEXT: br i1 [[TMP5]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
575 ; VEC: pred.store.if:
576 ; VEC-NEXT: [[TMP6:%.*]] = extractelement <2 x i8> [[WIDE_LOAD]], i32 0
577 ; VEC-NEXT: [[TMP7:%.*]] = zext i8 [[TMP6]] to i32
578 ; VEC-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i8
579 ; VEC-NEXT: [[TMP9:%.*]] = getelementptr i8, i8* undef, i64 [[TMP0]]
580 ; VEC-NEXT: store i8 [[TMP8]], i8* [[TMP9]], align 1
581 ; VEC-NEXT: br label [[PRED_STORE_CONTINUE]]
582 ; VEC: pred.store.continue:
583 ; VEC-NEXT: [[TMP10:%.*]] = extractelement <2 x i1> [[BROADCAST_SPLAT]], i32 1
584 ; VEC-NEXT: br i1 [[TMP10]], label [[PRED_STORE_IF2:%.*]], label [[PRED_STORE_CONTINUE3]]
585 ; VEC: pred.store.if2:
586 ; VEC-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 1
587 ; VEC-NEXT: [[TMP12:%.*]] = extractelement <2 x i8> [[WIDE_LOAD]], i32 1
588 ; VEC-NEXT: [[TMP13:%.*]] = zext i8 [[TMP12]] to i32
589 ; VEC-NEXT: [[TMP14:%.*]] = trunc i32 [[TMP13]] to i8
590 ; VEC-NEXT: [[TMP15:%.*]] = getelementptr i8, i8* undef, i64 [[TMP11]]
591 ; VEC-NEXT: store i8 [[TMP14]], i8* [[TMP15]], align 1
592 ; VEC-NEXT: br label [[PRED_STORE_CONTINUE3]]
593 ; VEC: pred.store.continue3:
594 ; VEC-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
595 ; VEC-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], undef
596 ; VEC-NEXT: br i1 [[TMP16]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOO…
597 ; VEC: middle.block:
598 ; VEC-NEXT: [[CMP_N:%.*]] = icmp eq i64 undef, undef
599 ; VEC-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[FOR_BODY:%.*]]
600 ; VEC: for.body:
601 ; VEC-NEXT: [[TMP0:%.*]] = phi i64 [ [[TMP6:%.*]], [[FOR_INC:%.*]] ], [ undef, [[MIDDLE_BLOCK]] ]
602 ; VEC-NEXT: [[TMP1:%.*]] = phi i64 [ [[TMP7:%.*]], [[FOR_INC]] ], [ undef, [[MIDDLE_BLOCK]] ]
603 ; VEC-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* undef, i64 [[TMP0]]
604 ; VEC-NEXT: [[TMP3:%.*]] = load i8, i8* [[TMP2]], align 1
605 ; VEC-NEXT: br i1 [[C]], label [[IF_THEN:%.*]], label [[FOR_INC]]
606 ; VEC: if.then:
607 ; VEC-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i32
608 ; VEC-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
609 ; VEC-NEXT: store i8 [[TMP5]], i8* [[TMP2]], align 1
610 ; VEC-NEXT: br label [[FOR_INC]]
611 ; VEC: for.inc:
612 ; VEC-NEXT: [[TMP6]] = add nuw nsw i64 [[TMP0]], 1
613 ; VEC-NEXT: [[TMP7]] = add i64 [[TMP1]], -1
614 ; VEC-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 0
615 ; VEC-NEXT: br i1 [[TMP8]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
616 ; VEC: for.end:
617 ; VEC-NEXT: ret void
728 ; VEC-LABEL: @minimal_bit_widths_with_aliasing_store(
729 ; VEC-NEXT: entry:
730 ; VEC-NEXT: br label [[FOR_BODY:%.*]]
731 ; VEC: for.body:
732 ; VEC-NEXT: [[TMP0:%.*]] = phi i64 [ [[TMP6:%.*]], [[FOR_INC:%.*]] ], [ 0, [[ENTRY:%.*]] ]
733 ; VEC-NEXT: [[TMP1:%.*]] = phi i64 [ [[TMP7:%.*]], [[FOR_INC]] ], [ 0, [[ENTRY]] ]
734 ; VEC-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[PTR:%.*]], i64 [[TMP0]]
735 ; VEC-NEXT: [[TMP3:%.*]] = load i8, i8* [[TMP2]], align 1
736 ; VEC-NEXT: store i8 0, i8* [[TMP2]], align 1
737 ; VEC-NEXT: br i1 [[C:%.*]], label [[IF_THEN:%.*]], label [[FOR_INC]]
738 ; VEC: if.then:
739 ; VEC-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i32
740 ; VEC-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
741 ; VEC-NEXT: store i8 [[TMP5]], i8* [[TMP2]], align 1
742 ; VEC-NEXT: br label [[FOR_INC]]
743 ; VEC: for.inc:
744 ; VEC-NEXT: [[TMP6]] = add nuw nsw i64 [[TMP0]], 1
745 ; VEC-NEXT: [[TMP7]] = add i64 [[TMP1]], -1
746 ; VEC-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 0
747 ; VEC-NEXT: br i1 [[TMP8]], label [[FOR_END:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]…
748 ; VEC: for.end:
749 ; VEC-NEXT: ret void