Home
last modified time | relevance | path

Searched refs:VDUP (Results 1 – 9 of 9) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleR52.td798 def : InstRW<[R52WriteFPALU_F3, R52Read_ISS], (instregex "VDUP(8|16|32)d")>;
799 def : InstRW<[R52Write2FPALU_F3, R52Read_ISS], (instregex "VDUP(8|16|32)q")>;
H A DARMISelLowering.h199 VDUP, enumerator
H A DARMISelLowering.cpp1759 MAKE_CASE(ARMISD::VDUP) in getTargetNodeName()
7820 SDValue VDup = DAG.getNode(ARMISD::VDUP, dl, DupVT, Const); in LowerBUILD_VECTOR()
7949 N = DAG.getNode(ARMISD::VDUP, dl, VT, Value); in LowerBUILD_VECTOR()
7983 return DAG.getNode(ARMISD::VDUP, dl, VT, Val); in LowerBUILD_VECTOR()
13852 if (VDup->getOpcode() != ARMISD::VDUP) in PerformSUBCombine()
15219 if (Op0->getOpcode() == ARMISD::VDUP && Op1->getOpcode() != ARMISD::VDUP) in PerformVCMPCombine()
15327 if (Op0->getOpcode() == ARMISD::VDUP) { in PerformExtractEltCombine()
16264 return DCI.DAG.getNode(ARMISD::VDUP, SDLoc(N), VT, Extract); in PerformVDUPLANECombine()
16302 return DAG.getNode(ARMISD::VDUP, dl, N->getValueType(0), in PerformVDUPCombine()
16305 return DAG.getNode(ARMISD::VDUP, dl, N->getValueType(0), in PerformVDUPCombine()
[all …]
H A DARMScheduleSwift.td635 (instregex "VDUP(8|16|32)")>;
H A DARM.td255 // True if VMOV will be favored over VDUP.
H A DARMScheduleA57.td1203 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "VDUP(8|16|32)(d|q)")>;
H A DARMInstrNEON.td6625 // VDUP : Vector Duplicate (from ARM core register to all elements)
6644 // ARMvdup patterns for uarchs with fast VDUP.32.
6650 // ARMvdup patterns for uarchs with slow VDUP.32 - use VMOVDRR instead.
6656 // VDUP : Vector Duplicate Lane (from scalar to all elements)
H A DARMISelDAGToDAG.cpp3202 case ARMISD::VDUP: { in transformFixedFloatingPointConversion()
H A DARMInstrInfo.td256 def ARMvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;