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Searched refs:VCTP (Results 1 – 13 of 13) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
H A Dvector-reduce-mve-tail.ll12 ; CHECK: [[VCTP:%[^ ]+]] = call <4 x i1> @llvm.arm.mve.vctp32(i32 [[ELTS]])
14 ; CHECK: call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* {{.*}}, i32 4, <4 x i1> [[VCTP]]
15 ; CHECK: call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* {{.*}}, i32 4, <4 x i1> [[VCTP]],
18 ; CHECK: [[VPSEL:%[^ ]+]] = select <4 x i1> [[VCTP]],
H A Dtail-pred-basic.ll8 ; CHECK: [[VCTP:%[^ ]+]] = call <16 x i1> @llvm.arm.mve.vctp8(i32 [[ELEMS]])
12 …id @llvm.masked.store.v16i8.p0v16i8(<16 x i8> {{.*}}, <16 x i8>* {{.*}}, i32 4, <16 x i1> [[VCTP]])
56 ; CHECK: [[VCTP:%[^ ]+]] = call <8 x i1> @llvm.arm.mve.vctp16(i32 [[ELEMS]])
60 …oid @llvm.masked.store.v8i16.p0v8i16(<8 x i16> {{.*}}, <8 x i16>* {{.*}}, i32 4, <8 x i1> [[VCTP]])
103 ; CHECK: [[VCTP:%[^ ]+]] = call <4 x i1> @llvm.arm.mve.vctp32(i32 [[ELEMS]])
107 …oid @llvm.masked.store.v4i32.p0v4i32(<4 x i32> {{.*}}, <4 x i32>* {{.*}}, i32 4, <4 x i1> [[VCTP]])
151 ; CHECK: [[VCTP:%[^ ]+]] = call <4 x i1> @llvm.arm.mve.vctp32(i32 [[ELEMS]])
155 …oid @llvm.masked.store.v4i32.p0v4i32(<4 x i32> {{.*}}, <4 x i32>* {{.*}}, i32 4, <4 x i1> [[VCTP]])
203 ; CHECK: [[VCTP:%[^ ]+]] = call <4 x i1> @llvm.arm.mve.vctp32(i32 [[ELEMS]])
207 …oid @llvm.masked.store.v4i32.p0v4i32(<4 x i32> {{.*}}, <4 x i32>* {{.*}}, i32 4, <4 x i1> [[VCTP]])
[all …]
H A Dtail-pred-reduce.ll8 ; CHECK: [[VCTP:%[^ ]+]] = call <8 x i1> @llvm.arm.mve.vctp16(i32 [[PHI]])
10 ; CHECK: call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp4, i32 4, <8 x i1> [[VCTP]],…
11 ; CHECK: call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp6, i32 4, <8 x i1> [[VCTP]],…
70 ; CHECK: [[VCTP:%[^ ]+]] = call <8 x i1> @llvm.arm.mve.vctp16(i32 [[PHI]])
72 ; CHECK: call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp4, i32 4, <8 x i1> [[VCTP]],…
H A Dlsr-profitable-chain.ll7 ; Tests that LSR will not interfere with the VCTP intrinsic,
H A Dtail-pred-widen.ll47 ; CHECK: [[VCTP:%[^ ]+]] = call <8 x i1> @llvm.arm.mve.vctp16(i32 [[ELEMS]])
49 … i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* {{.*}}, i32 4, <8 x i1> [[VCTP]], <8 x i16> undef)
H A Dwrong-vctp-operand-liveout.mir4 # The VCTP uses r2, which is redefined in the loop.
H A Div-two-vcmp-reordered.mir4 # TODO: We should be able to handle the VCMP -> VPST -> VCMP -> VCTP case.
H A Dvpt-blocks.mir369 ; VCTP's.
498 …ts that secondary VCTPs are refused when their operand is not the same register as the main VCTP's.
618 ; Test including a else-predicated VCTP.
969 ; This shouldn't be tail-predicated because the VLDR isn't predicated on the VCTP.
H A Dwls-revert-placement.mir5 # should not crash or leave any VCTP instructions.
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMLowOverheadLoops.cpp639 MachineInstr *VCTP = VCTPs.back(); in ValidateTailPredicate() local
646 TPNumElements = VCTP->getOperand(1); in ValidateTailPredicate()
652 if (RDA.hasLocalDefBefore(VCTP, NumElements)) { in ValidateTailPredicate()
743 unsigned VCTPVecSize = getVecSize(*VCTP); in ValidateTailPredicate()
761 MachineBasicBlock *MBB = VCTP->getParent(); in ValidateTailPredicate()
767 &MBB->back(), VCTP->getOperand(1).getReg().asMCReg())) { in ValidateTailPredicate()
770 unsigned ExpectedVectorWidth = getTailPredVectorWidth(VCTP->getOpcode()); in ValidateTailPredicate()
804 !RDA.hasLocalDefBefore(VCTP, VCTP->getOperand(1).getReg())) { in ValidateTailPredicate()
806 &Preheader->back(), VCTP->getOperand(1).getReg().asMCReg())) { in ValidateTailPredicate()
H A DMVETailPredication.cpp380 Function *VCTP = Intrinsic::getDeclaration(M, VCTPID); in InsertVCTPIntrinsic() local
381 Value *VCTPCall = Builder.CreateCall(VCTP, Processed); in InsertVCTPIntrinsic()
H A DMVETPAndVPTOptimisationsPass.cpp469 for (MachineInstr *VCTP : VCTPs) { in ConvertTailPredLoop()
470 LLVM_DEBUG(dbgs() << " with VCTP " << *VCTP); in ConvertTailPredLoop()
471 if (VCTP->getOpcode() != FirstVCTP->getOpcode() || in ConvertTailPredLoop()
472 VCTP->getOperand(0).getReg() != FirstVCTP->getOperand(0).getReg()) { in ConvertTailPredLoop()
/llvm-project-15.0.7/llvm/lib/IR/
H A DAutoUpgrade.cpp1872 Value *VCTP = Builder.CreateCall( in UpgradeARMIntrinsicCall() local
1879 VCTP); in UpgradeARMIntrinsicCall()