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/llvm-project-15.0.7/clang/test/Preprocessor/
H A Dprint-pragma-microsoft.c12 #define VAL2 "VAL2" macro
14 #pragma detect_mismatch(KEY1 KEY2, VAL1 VAL2)
/llvm-project-15.0.7/clang/test/CodeGen/
H A Dbuiltins-bpf-preserve-field-info-4.c9 VAL2 = 0xffffffff80000000UL, enumerator
18 return _(*(enum AA *)VAL2, 0) + _(*(__BB *)VAL11, 1); in unit2()
H A Dbuiltins-bpf-preserve-field-info-3.c12 VAL2 = 2, enumerator
/llvm-project-15.0.7/flang/test/Fir/
H A Dglobal-initialization.fir14 // CHECK: [[VAL2:%.*]] = llvm.mlir.constant(dense<1> : vector<32xi32>) : !llvm.array<32 x i32>
15 // CHECK: llvm.return [[VAL2]] : !llvm.array<32 x i32>
28 // CHECK: [[VAL2:%.*]] = llvm.mlir.constant(dense<1> : vector<32x32xi32>) : !llvm.array<32 x arra…
29 // CHECK: llvm.return [[VAL2]] : !llvm.array<32 x array<32 x i32>>
43 // CHECK: [[VAL2:%.*]] = llvm.zext [[VAL0]] : i1 to i32
/llvm-project-15.0.7/llvm/test/Transforms/ObjCARC/
H A Dintrinsic-use.ll30 ; CHECK-NEXT: [[VAL2:%.*]] = load i8*, i8** %temp1
31 ; CHECK-NEXT: @llvm.objc.retain(i8* [[VAL2]])
37 ; CHECK-NEXT: @llvm.objc.release(i8* [[VAL2]])
78 ; CHECK-NEXT: [[VAL2:%.*]] = load i8*, i8** %temp1
79 ; CHECK-NEXT: @llvm.objc.retain(i8* [[VAL2]])
83 ; CHECK-NEXT: @llvm.objc.release(i8* [[VAL2]])
/llvm-project-15.0.7/llvm/test/CodeGen/BPF/CORE/
H A Dintrinsic-typeinfo-enum-value.ll6 ; enum AA { VAL1 = -100, VAL2 = 0xffff8000 };
10 ; __builtin_preserve_enum_value(*(enum AA *)VAL2, 1) +
19 @1 = private unnamed_addr constant [16 x i8] c"VAL2:4294934528\00", align 1
61 ; CHECK: .ascii "VAL2" # string offset=24
100 !7 = !DIEnumerator(name: "VAL2", value: 4294934528)
H A Dintrinsic-typeinfo-enum-value-opaque-pointer.ll6 ; enum AA { VAL1 = -100, VAL2 = 0xffff8000 };
10 ; __builtin_preserve_enum_value(*(enum AA *)VAL2, 1) +
19 @1 = private unnamed_addr constant [16 x i8] c"VAL2:4294934528\00", align 1
81 !7 = !DIEnumerator(name: "VAL2", value: 4294934528)
/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/
H A Dwrong-hoisting-iv.ll14 ; CHECK-NEXT: [[VAL2:%.*]] = trunc i64 undef to i32
15 ; CHECK-NEXT: [[VAL3:%.*]] = mul i32 [[VAL1]], [[VAL2]]
48 ; CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[VAL1]], [[VAL2]]
60 ; CHECK-NEXT: [[TMP15:%.*]] = mul i32 [[VAL1]], [[VAL2]]
72 ; CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[VAL1]], [[VAL2]]
84 ; CHECK-NEXT: [[TMP29:%.*]] = mul i32 [[VAL1]], [[VAL2]]
96 ; CHECK-NEXT: [[TMP36:%.*]] = mul i32 [[VAL1]], [[VAL2]]
195 ; CHECK-NEXT: [[VAL2:%.*]] = bitcast i8* null to i32*
196 ; CHECK-NEXT: [[VAL3:%.*]] = load i32, i32* [[VAL2]], align 4
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-2012-05-07-MemcpyAlignBug.ll11 ; CHECK-NEXT: ldr [[VAL2:x[0-9]+]], [x[[ADDR]]]
14 ; CHECK-NEXT: str [[VAL2]], [x0]
H A Dlarge-stack.ll38 ; CHECK-NEXT: mov x[[VAL2:[0-9]+]], #8
39 ; CHECK-NEXT: madd x[[VAL1]], x[[VAL1]], x[[VAL2]], x[[VAL3]]
H A Darm64-virtual_base.ll36 ; CHECK: ldr [[VAL2:q[0-9]+]], [x0, #272]
38 ; CHECK-NEXT: stur [[VAL2]], [sp, #216]
/llvm-project-15.0.7/clang/test/Sema/
H A Dbuiltins-bpf.c20 VAL2 = 0xffffffff80000000UL, enumerator
91 __builtin_preserve_enum_value(*(enum AA *)VAL2, 1); in valid15()
/llvm-project-15.0.7/llvm/test/Transforms/Scalarizer/
H A Dconstant-extractelement.ll12 ; ALL-NEXT: [[VAL2:%.*]] = shl i32 4, [[VAL0_I3]]
13 ; ALL-NEXT: ret i32 [[VAL2]]
H A Dvariable-extractelement.ll51 ; DEFAULT-NEXT: [[VAL2:%.*]] = select i1 [[INDEX_IS_3]], i32 [[VAL1_I3]], i32 [[VAL2_UPTO2]]
52 ; DEFAULT-NEXT: ret i32 [[VAL2]]
68 ; OFF-NEXT: [[VAL2:%.*]] = extractelement <4 x i32> [[VAL1]], i32 [[INDEX:%.*]]
69 ; OFF-NEXT: ret i32 [[VAL2]]
H A Dvariable-insertelement.ll59 ; DEFAULT-NEXT: [[VAL2:%.*]] = insertelement <4 x i32> [[VAL2_UPTO2]], i32 [[VAL2_I3]], i32 3
60 ; DEFAULT-NEXT: store <4 x i32> [[VAL2]], <4 x i32>* [[DEST:%.*]], align 16
77 ; OFF-NEXT: [[VAL2:%.*]] = insertelement <4 x i32> [[VAL2_UPTO2]], i32 [[VAL2_I3]], i32 3
78 ; OFF-NEXT: store <4 x i32> [[VAL2]], <4 x i32>* [[DEST:%.*]], align 16
H A Dconstant-insertelement.ll22 ; ALL-NEXT: [[VAL2:%.*]] = insertelement <4 x i32> [[VAL2_UPTO2]], i32 [[VAL2_I3]], i32 3
23 ; ALL-NEXT: ret <4 x i32> [[VAL2]]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Daggregate-padding.ll82 ; CHECK: ldrh [[VAL2:r[0-9]+]], [sp]
83 ; CHECK: add r0, r2, [[VAL2]]
95 ; CHECK-DAG: ldrh [[VAL2:r[0-9]+]], [sp, #16]
96 ; CHECK: add r0, [[VAL0]], [[VAL2]]
/llvm-project-15.0.7/llvm/test/Transforms/LoadStoreVectorizer/X86/
H A Dnon-byte-size.ll14 ; CHECK-NEXT: [[VAL2:%.*]] = load i28, i28* [[IN2]]
18 ; CHECK-NEXT: store i28 [[VAL2]], i28* [[OUT2]]
/llvm-project-15.0.7/llvm/test/TableGen/
H A DDag.td30 def VAL2 : C2<Y2>;
32 // CHECK: def VAL2 {
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dannotate-kernel-features.ll166 ; AKF_CHECK-NEXT: [[VAL2:%.*]] = call i32 @llvm.r600.read.tgid.z()
169 ; AKF_CHECK-NEXT: store volatile i32 [[VAL2]], i32 addrspace(1)* [[PTR]], align 4
176 ; ATTRIBUTOR_CHECK-NEXT: [[VAL2:%.*]] = call i32 @llvm.r600.read.tgid.z()
179 ; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL2]], i32 addrspace(1)* [[PTR]], align 4
284 ; AKF_CHECK-NEXT: [[VAL2:%.*]] = call i32 @llvm.r600.read.tidig.z()
287 ; AKF_CHECK-NEXT: store volatile i32 [[VAL2]], i32 addrspace(1)* [[PTR]], align 4
294 ; ATTRIBUTOR_CHECK-NEXT: [[VAL2:%.*]] = call i32 @llvm.r600.read.tidig.z()
297 ; ATTRIBUTOR_CHECK-NEXT: store volatile i32 [[VAL2]], i32 addrspace(1)* [[PTR]], align 4
314 ; AKF_CHECK-NEXT: [[VAL2:%.*]] = call i32 @llvm.r600.read.tidig.z()
320 ; AKF_CHECK-NEXT: store volatile i32 [[VAL2]], i32 addrspace(1)* [[PTR]], align 4
[all …]
H A Dannotate-kernel-features-hsa.ll171 ; AKF_HSA-NEXT: [[VAL2:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z()
174 ; AKF_HSA-NEXT: store volatile i32 [[VAL2]], i32 addrspace(1)* [[PTR]], align 4
181 ; ATTRIBUTOR_HSA-NEXT: [[VAL2:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z()
184 ; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL2]], i32 addrspace(1)* [[PTR]], align 4
289 ; AKF_HSA-NEXT: [[VAL2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()
292 ; AKF_HSA-NEXT: store volatile i32 [[VAL2]], i32 addrspace(1)* [[PTR]], align 4
299 ; ATTRIBUTOR_HSA-NEXT: [[VAL2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()
302 ; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL2]], i32 addrspace(1)* [[PTR]], align 4
319 ; AKF_HSA-NEXT: [[VAL2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()
325 ; AKF_HSA-NEXT: store volatile i32 [[VAL2]], i32 addrspace(1)* [[PTR]], align 4
[all …]
H A Dconstant-fold-imm-immreg.mir54 # GCN: [[VAL2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 646, implicit $exec
55 # GCN: FLAT_STORE_DWORD %10, [[VAL2]],
168 # GCN: [[VAL2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1678031, implicit $exec
169 # GCN: FLAT_STORE_DWORD %10, [[VAL2]],
292 # GCN: [[VAL2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1678031, implicit $exec
293 # GCN: FLAT_STORE_DWORD %10, [[VAL2]],
/llvm-project-15.0.7/mlir/test/Conversion/GPUToSPIRV/
H A Dload-store.mlir74 // CHECK-NEXT: %[[VAL2:.*]] = spv.Load "StorageBuffer" %[[PTR2]]
76 // CHECK: %[[VAL3:.*]] = spv.FAdd %[[VAL1]], %[[VAL2]]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dpr44242.ll152 ; CHECK-NEXT: [[VAL:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[VAL2:%.*]], [[LOOP_END:%.*]] ]
164 ; CHECK-NEXT: [[VAL2]] = phi i32 [ [[VAL]], [[LOOP]] ], [ [[VAL_INCR_CASTED]], [[IF]] ]
165 ; CHECK-NEXT: store volatile i32 [[VAL2]], i32* @global, align 4
/llvm-project-15.0.7/llvm/test/Transforms/GVN/
H A Dduplicate-phis.ll86 ; CHECK-NEXT: [[VAL2:%.*]] = phi i32 [ [[VAL2_INC:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
91 ; CHECK-NEXT: [[VAL2_INC]] = add i32 [[VAL2]], 1

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