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/llvm-project-15.0.7/llvm/test/Object/
H A Dnm-tapi.test8 RUN: | FileCheck %s -check-prefix V3
35 V3: /usr/lib/libfoo.dylib (for architecture x86_64):
37 V3-NEXT: 0000000000000000 S _OBJC_CLASS_$_NSString
38 V3-NEXT: 0000000000000000 S _OBJC_EHTYPE_$_NSString
42 V3-NEXT: 0000000000000000 S _sym1
43 V3-NEXT: 0000000000000000 S _sym2
44 V3: /usr/lib/liba.dylib (for architecture x86_64):
46 V3-NEXT: 0000000000000000 S _OBJC_CLASS_$_NSString
47 V3-NEXT: 0000000000000000 S _OBJC_EHTYPE_$_NSString
51 V3-NEXT: 0000000000000000 S _sym1
[all …]
H A Dnm-tapi-invalids.test8 RUN: | FileCheck %s -check-prefix V3
19 V3: tapi-invalid-v3.tbd: malformed file
20 V3-NEXT: tapi-invalid-v3.tbd:19:1: error: unknown key 'swift-version'
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Ddirective-amdgcn-target.ll193 ; V3-GFX600: .amdgcn_target "amdgcn-amd-amdhsa--gfx600"
194 ; V3-GFX601: .amdgcn_target "amdgcn-amd-amdhsa--gfx601"
195 ; V3-GFX602: .amdgcn_target "amdgcn-amd-amdhsa--gfx602"
196 ; V3-GFX700: .amdgcn_target "amdgcn-amd-amdhsa--gfx700"
197 ; V3-GFX701: .amdgcn_target "amdgcn-amd-amdhsa--gfx701"
198 ; V3-GFX702: .amdgcn_target "amdgcn-amd-amdhsa--gfx702"
199 ; V3-GFX703: .amdgcn_target "amdgcn-amd-amdhsa--gfx703"
200 ; V3-GFX704: .amdgcn_target "amdgcn-amd-amdhsa--gfx704"
201 ; V3-GFX705: .amdgcn_target "amdgcn-amd-amdhsa--gfx705"
204 ; V3-GFX802: .amdgcn_target "amdgcn-amd-amdhsa--gfx802"
[all …]
H A Dtrap-abis.ll29 ; NOHSA-TRAP-GFX900-V3-LABEL: trap:
30 ; NOHSA-TRAP-GFX900-V3: ; %bb.0:
37 ; NOHSA-TRAP-GFX900-V3-NEXT: s_endpgm
129 ; HSA-TRAP-GFX803-V3-LABEL: trap:
130 ; HSA-TRAP-GFX803-V3: ; %bb.0:
139 ; HSA-TRAP-GFX803-V3-NEXT: s_trap 2
232 ; HSA-TRAP-GFX900-V3-LABEL: trap:
233 ; HSA-TRAP-GFX900-V3: ; %bb.0:
331 ; HSA-NOTRAP-GFX900-V3-LABEL: trap:
917 ; HSA-TRAP-GFX803-V3: ; %bb.0:
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dthumb2-ifcvt1.ll65 ; V3-LABEL: t2:
67 ; V3-NEXT: cmp r0, r1
68 ; V3-NEXT: it eq
69 ; V3-NEXT: bxeq lr
72 ; V3-NEXT: cmp r0, r1
73 ; V3-NEXT: ite le
76 ; V3-NEXT: cmp r1, r0
79 ; V3-NEXT: bx lr
169 ; V3-NEXT: it eq
170 ; V3-NEXT: bxeq lr
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dvec_perf_shuffle.ll8 …%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 undef, i32 undef, i32 7, i32…
9 ret <4 x float> %V3
15 …%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 0, i32 undef, i32 5 >…
16 ret <4 x float> %V3
22 …%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 undef, i32 7, i32 3 >…
23 ret <4 x float> %V3
29 …%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 7, i32 7, i32 4 > ; …
30 ret <4 x float> %V3
36 …%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 4, i32 4, i32 5, i32 0 > ; …
37 ret <4 x float> %V3
/llvm-project-15.0.7/llvm/unittests/ADT/
H A DSTLExtrasTest.cpp640 EXPECT_EQ(V3.get(), llvm::to_address(V3)); in TEST()
643 V3.reset(V1); in TEST()
676 EXPECT_TRUE(hasNItems(V3.begin(), V3.end(), 3, [](int x) { return x < 10; })); in TEST()
678 EXPECT_TRUE(hasNItems(V3.begin(), V3.end(), 2, [](int x) { return x < 5; })); in TEST()
696 hasNItemsOrMore(V3.begin(), V3.end(), 3, [](int x) { return x < 10; })); in TEST()
698 hasNItemsOrMore(V3.begin(), V3.end(), 3, [](int x) { return x > 10; })); in TEST()
700 hasNItemsOrMore(V3.begin(), V3.end(), 2, [](int x) { return x < 5; })); in TEST()
727 hasNItemsOrLess(V3.begin(), V3.end(), 1, [](int x) { return x == 1; })); in TEST()
729 hasNItemsOrLess(V3.begin(), V3.end(), 2, [](int x) { return x < 5; })); in TEST()
731 hasNItemsOrLess(V3.begin(), V3.end(), 5, [](int x) { return x < 5; })); in TEST()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/BPF/
H A Datomics.ll2 …march=bpfel -verify-machineinstrs -show-mc-encoding -mcpu=v3 | FileCheck --check-prefix=CHECK-V3 %s
7 ; CHECK-V3: lock *(u32 *)(r1 + 0) += w2
8 ; CHECK-V3: encoding: [0xc3,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
18 ; CHECK-V3: lock *(u64 *)(r1 + 0) += r2
19 ; CHECK-V3: encoding: [0xdb,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
/llvm-project-15.0.7/mlir/test/Target/Cpp/
H A Dcommon-cpp.mlir14 // CHECK: [[V3:[^ ]*]] = foo::op_and_attr([[V2]], {0, 1});
16 // CHECK: foo::print([[V3]]);
29 // CHECK: std::tie([[V3:.*]], [[V4:.*]]) = foo::blah();
31 // CHECK: [[V5:[^ ]*]] = test_single_return([[V3]]);
76 // CHECK: int [[V3:[^ ]*]] = a([[V1]], [[V2]]);
78 // CHECK: char [[V4:[^ ]*]] = b([[V3]]);
80 // CHECK: status_t [[V5:[^ ]*]] = c([[V3]], [[V4]]);
88 // CHECK: int32_t [[V3]] = *[[V2]];
H A Dif.mlir39 // CPP-DEFAULT-NEXT: int32_t [[V3:[^ ]*]] = func_false([[V1]]);
46 // CPP-DECLTOP-NEXT: int32_t [[V3:[^ ]*]];
51 // CPP-DECLTOP-NEXT: [[V3]] = func_false([[V1]]);
72 // CPP-DEFAULT-NEXT: int32_t [[V3:[^ ]*]];
77 // CPP-DEFAULT-NEXT: [[V3]] = [[V5]];
82 // CPP-DEFAULT-NEXT: [[V3]] = [[V7]];
89 // CPP-DECLTOP-NEXT: int32_t [[V3:[^ ]*]];
99 // CPP-DECLTOP-NEXT: [[V3]] = [[V5]];
104 // CPP-DECLTOP-NEXT: [[V3]] = [[V7]];
H A Dcall.mlir28 // CPP-DEFAULT-NEXT: int32_t [[V3:[^ ]*]];
29 // CPP-DEFAULT-NEXT: std::tie([[V2]], [[V3]]) = two_results();
34 // CPP-DECLTOP-NEXT: int32_t [[V3:[^ ]*]];
36 // CPP-DECLTOP-NEXT: std::tie([[V2]], [[V3]]) = two_results();
H A Dstdops.mlir17 // CPP-DEFAULT-NEXT: Tensor<int32_t> [[V3:[^ ]*]] = {0};
25 // CPP-DECLTOP-NEXT: Tensor<int32_t> [[V3:[^ ]*]];
31 // CPP-DECLTOP-NEXT: [[V3]] = {0};
62 // CPP-DEFAULT-NEXT: int32_t [[V3:[^ ]*]];
64 // CPP-DEFAULT-NEXT: std::tie([[V3]], [[V4]]) = two_results();
70 // CPP-DECLTOP-NEXT: int32_t [[V3:[^ ]*]];
74 // CPP-DECLTOP-NEXT: std::tie([[V3]], [[V4]]) = two_results();
/llvm-project-15.0.7/libcxx/test/std/ranges/range.req/range.view/
H A Denable_view.compile.pass.cpp88 struct V3 : std::ranges::view_interface<V1> {}; struct
89 static_assert(std::ranges::enable_view<V3>);
90 static_assert(!std::ranges::enable_view<V3&>);
91 static_assert(!std::ranges::enable_view<V3&&>);
92 static_assert(std::ranges::enable_view<const V3>);
93 static_assert(!std::ranges::enable_view<const V3&>);
94 static_assert(!std::ranges::enable_view<const V3&&>);
/llvm-project-15.0.7/llvm/test/MC/Hexagon/
H A Dv67_all.s4 V3:0.w=vrmpyz(v0.b,r0.ub)
6 V3:0.w+=vrmpyz(v0.b,r0.ub)
8 V3:0.w=vrmpyz(v0.b,r0.ub++)
10 V3:0.w+=vrmpyz(v0.b,r0.ub++)
/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Dvtt-layout.cpp32 class V3 {virtual void g(); }; class
34 class C2 : public virtual V3, virtual V2 { int i; };
51 class V3 {virtual void g(); }; class
53 class C2 : public virtual V3, virtual V2 { int i; };
/llvm-project-15.0.7/llvm/lib/Support/
H A Dxxhash.cpp81 uint64_t V3 = Seed + 0; in xxHash64() local
89 V3 = round(V3, endian::read64le(P)); in xxHash64()
95 H64 = rotl64(V1, 1) + rotl64(V2, 7) + rotl64(V3, 12) + rotl64(V4, 18); in xxHash64()
98 H64 = mergeRound(H64, V3); in xxHash64()
/llvm-project-15.0.7/clang/test/CodeGenObjC/
H A Dstrong-in-c-struct.m129 // CHECK: %[[V3:.*]] = bitcast i8* %[[V2]] to i8**
130 // CHECK: %[[V4:.*]] = bitcast i8** %[[V3]] to i8*
140 // CHECK: %[[V3:.*]] = bitcast i8* %[[V2]] to i8**
141 // CHECK: %[[V4:.*]] = bitcast i8** %[[V3]] to i8*
152 // CHECK: %[[V3:.*]] = bitcast i8* %[[V2]] to i8**
162 // CHECK: %[[V3:.*]] = bitcast i8* %[[V2]] to i8**
192 // CHECK: %[[V4:.*]] = bitcast i8* %[[V3]] to i8**
219 // CHECK: %[[V3:.*]] = bitcast i8** %[[V1]] to i8*
245 // CHECK: %[[V4:.*]] = bitcast i8* %[[V3]] to i8**
277 // CHECK: %[[V4:.*]] = bitcast i8* %[[V3]] to i8**
[all …]
H A Dweak-in-c-struct.m32 // ARM64: %[[V3:.*]] = bitcast i8* %[[V2]] to i8**
33 // ARM64: %[[V4:.*]] = bitcast i8** %[[V3]] to i8*
42 // ARM64: %[[V3:.*]] = bitcast i8* %[[V2]] to i8**
43 // ARM64: call void @llvm.objc.destroyWeak(i8** %[[V3]])
65 // ARM64: %[[V3:.*]] = bitcast i8** %[[V1]] to i32*
66 // ARM64: %[[V4:.*]] = load i32, i32* %[[V3]], align 8
91 // ARM64: %[[V3:.*]] = bitcast i8** %[[V1]] to i32*
92 // ARM64: %[[V4:.*]] = load i32, i32* %[[V3]], align 8
119 // ARM64: %[[V3:.*]] = bitcast i8** %[[V1]] to i32*
120 // ARM64: %[[V4:.*]] = load i32, i32* %[[V3]], align 8
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Vector/
H A Dvector-multi-reduction-outer-lowering.mlir17 // CHECK: %[[V3:.+]] = vector.extract %[[TRANSPOSED]][3] : vector<4x2xf32>
18 // CHECK: %[[RESULT_VEC:.+]] = arith.mulf %[[V3]], %[[RV012]] : vector<2xf32>
35 // CHECK: %[[V3:.+]] = vector.extract %[[TRANSPOSED]][3] : vector<4x2xf32>
36 // CHECK: %[[RESULT_VEC:.+]] = arith.minf %[[V3]], %[[RV012]] : vector<2xf32>
53 // CHECK: %[[V3:.+]] = vector.extract %[[TRANSPOSED]][3] : vector<4x2xf32>
54 // CHECK: %[[RESULT_VEC:.+]] = arith.maxf %[[V3]], %[[RV012]] : vector<2xf32>
71 // CHECK: %[[V3:.+]] = vector.extract %[[TRANSPOSED]][3] : vector<4x2xi32>
89 // CHECK: %[[V3:.+]] = vector.extract %[[TRANSPOSED]][3] : vector<4x2xi32>
107 // CHECK: %[[V3:.+]] = vector.extract %[[TRANSPOSED]][3] : vector<4x2xi32>
128 // CHECK: %[[V3:.+]] = vector.extract %[[RESHAPED]][3] : vector<20x6xi32>
[all …]
/llvm-project-15.0.7/llvm/unittests/Support/
H A DAlignOfTest.cpp63 struct V3 : V1 { struct
64 ~V3() override;
69 struct V5 : V4, V3 { double z;
84 V3::~V3() {} in ~V3()
167 EXPECT_EQ(alignof(V3), alignof(AlignedCharArrayUnion<V3>)); in TEST()
232 EXPECT_EQ(sizeof(V3), sizeof(AlignedCharArrayUnion<V3>)); in TEST()
/llvm-project-15.0.7/clang/test/Driver/
H A Dhip-code-object-version.hip24 // RUN: %s 2>&1 | FileCheck -check-prefixes=V3,V3-WARN %s
29 // RUN: %s 2>&1 | FileCheck -check-prefix=V3 %s
34 // RUN: %s 2>&1 | FileCheck -check-prefix=V3 %s
36 // V3-WARN: warning: argument '-mcode-object-v3' is deprecated, use '-mcode-object-version=3' inste…
37 // V3: "-mcode-object-version=3"
38 // V3: "-mllvm" "--amdhsa-code-object-version=3"
39 // V3: "-targets=host-x86_64-unknown-linux,hip-amdgcn-amd-amdhsa--gfx906"
/llvm-project-15.0.7/mlir/test/Dialect/SCF/
H A Dparallel-loop-tiling.mlir24 // CHECK: scf.parallel ([[V3:%.*]], [[V4:%.*]]) = ([[ARG1]], [[ARG2]]) to ([[ARG3]], [[AR…
25 // CHECK: [[V5:%.*]] = affine.min #map([[V1]], [[ARG3]], [[V3]])
28 // CHECK: [[V9:%.*]] = arith.addi [[V7]], [[V3]] : index
60 // CHECK: scf.parallel ([[V3:%.*]], [[V4:%.*]]) = ([[C0]], [[C0]]) to ([[C22]], [[C24]]) …
62 // CHECK: = arith.addi [[V5]], [[V3]] : index
91 // CHECK: [[V3:%.*]] = arith.muli [[C1]], [[C1_1]] : index
93 …cf.parallel ([[V5:%.*]], [[V6:%.*]]) = ([[C0]], [[C0]]) to ([[C2]], [[C2]]) step ([[V3]], [[V4]]) {
95 // CHECK: scf.parallel ([[V8:%.*]], [[V9:%.*]]) = ([[C0_1]], [[C0_1]]) to ([[V3]], [[…
H A Dparallel-loop-tiling-inbound-check.mlir23 // CHECK: scf.parallel ([[V3:%.*]], [[V4:%.*]]) = ([[ARG1]], [[ARG2]]) to ([[ARG3]], [[AR…
25 // CHECK: [[V9:%.*]] = arith.addi [[V7]], [[V3]] : index
29 // CHECK: [[V12:%.*]] = arith.addi [[V11]], [[V3]] : index
68 // CHECK: scf.parallel ([[V3:%.*]], [[V4:%.*]]) = ([[C0]], [[C0]]) to ([[C22]], [[C24]]) …
71 // CHECK: = arith.addi [[V5]], [[V3]] : index
100 // CHECK: [[V3:%.*]] = arith.muli [[C1]], [[C1_1]] : index
102 …cf.parallel ([[V5:%.*]], [[V6:%.*]]) = ([[C0]], [[C0]]) to ([[C2]], [[C2]]) step ([[V3]], [[V4]]) {
103 // CHECK: scf.parallel ([[V8:%.*]], [[V9:%.*]]) = ([[C0_1]], [[C0_1]]) to ([[V3]], [[…
/llvm-project-15.0.7/clang/test/CodeGen/X86/
H A Dsse41-builtins.c29 __m128i test_mm_blendv_epi8(__m128i V1, __m128i V2, __m128i V3) { in test_mm_blendv_epi8() argument
32 return _mm_blendv_epi8(V1, V2, V3); in test_mm_blendv_epi8()
35 __m128d test_mm_blendv_pd(__m128d V1, __m128d V2, __m128d V3) { in test_mm_blendv_pd() argument
38 return _mm_blendv_pd(V1, V2, V3); in test_mm_blendv_pd()
41 __m128 test_mm_blendv_ps(__m128 V1, __m128 V2, __m128 V3) { in test_mm_blendv_ps() argument
44 return _mm_blendv_ps(V1, V2, V3); in test_mm_blendv_ps()
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dreduction-transpose.ll38 ; SSE2-NEXT: [[VECEXT16:%.*]] = extractelement <4 x i32> [[V3]], i64 1
39 ; SSE2-NEXT: [[VECEXT18:%.*]] = extractelement <4 x i32> [[V3]], i64 2
40 ; SSE2-NEXT: [[VECEXT20:%.*]] = extractelement <4 x i32> [[V3]], i64 3
90 ; AVX-NEXT: [[VECEXT16:%.*]] = extractelement <4 x i32> [[V3]], i64 1
91 ; AVX-NEXT: [[VECEXT18:%.*]] = extractelement <4 x i32> [[V3]], i64 2
92 ; AVX-NEXT: [[VECEXT20:%.*]] = extractelement <4 x i32> [[V3]], i64 3
163 ; SSE2-NEXT: [[VECEXT10:%.*]] = extractelement <4 x i32> [[V3]], i64 1
167 ; SSE2-NEXT: [[VECEXT18:%.*]] = extractelement <4 x i32> [[V3]], i64 2
213 ; AVX-NEXT: [[VECEXT10:%.*]] = extractelement <4 x i32> [[V3]], i64 1
217 ; AVX-NEXT: [[VECEXT18:%.*]] = extractelement <4 x i32> [[V3]], i64 2
[all …]

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