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/llvm-project-15.0.7/llvm/test/MC/Hexagon/
H A Dv62_all.s30 V0.b=vadd(V0.b,V0.b):sat
40 V0.w=vadd(V0.w,V0.w,Q0):carry
45 V0.h=vadd(vclb(V0.h),V0.h)
50 V0.w=vadd(vclb(V0.w),V0.w)
65 V0.ub=vadd(V0.ub,V0.b):sat
75 V0.uw=vadd(V0.uw,V0.uw):sat
105 V0.b=vasr(V0.h,V0.h,R0):sat
431 V0.b=vmax(V0.b,V0.b)
436 V0.b=vmin(V0.b,V0.b)
481 V0.uh=vsat(V0.uw,V0.uw)
[all …]
H A Dv65_all.s11 V0.uw+=vmpye(V0.uh,R0.uh)
21 vscatter(R0,M0,V0.w).w=V0
26 vscatter(R0,M0,V0.h).h=V0
31 V0.h=vlut4(V0.uh,R1:0.h)
71 V0.ub=vasr(V0.uh,V0.uh,R0):rnd:sat
86 V0.ub=vasr(V0.uh,V0.uh,R0):sat
101 V0.h=vmps(V0.h,V0.uh,R1:0.uh):sat
126 V0.uh=vasr(V0.uw,V0.uw,R0):sat
151 V0.b=vabs(V0.b)
166 V0.h=vmpa(V0.h,V0.uh,R1:0.uh):sat
[all …]
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Darmv8a-fpmul.s13 FMLAL V0.2S, V1.2H, V2.2H
14 FMLSL V0.2S, V1.2H, V2.2H
15 FMLAL V0.4S, V1.4H, V2.4H
16 FMLSL V0.4S, V1.4H, V2.4H
17 FMLAL2 V0.2S, V1.2H, V2.2H
18 FMLSL2 V0.2S, V1.2H, V2.2H
19 FMLAL2 V0.4S, V1.4H, V2.4H
20 FMLSL2 V0.4S, V1.4H, V2.4H
59 fmlal V0.2s, v1.2h, v2.h[7]
60 fmlsl V0.2s, v1.2h, v2.h[7]
[all …]
H A Darmv8a-fpmul-error.s7 fmlal V0.2s, v1.2h, v2.h[8]
8 fmlsl V0.2s, v1.2h, v2.h[8]
9 fmlal V0.4s, v1.4h, v2.h[8]
10 fmlsl V0.4s, v1.4h, v2.h[8]
12 fmlal2 V0.2s, v1.2h, v2.h[8]
13 fmlsl2 V0.2s, v1.2h, v2.h[8]
14 fmlal2 V0.4s, v1.4h, v2.h[8]
15 fmlsl2 V0.4s, v1.4h, v2.h[8]
17 fmlal V0.2s, v1.2h, v2.h[-1]
18 fmlsl2 V0.2s, v1.2h, v2.h[-1]
/llvm-project-15.0.7/mlir/test/Target/Cpp/
H A Dstdops.mlir22 // CPP-DECLTOP-NEXT: int32_t [[V0:[^ ]*]];
28 // CPP-DECLTOP-NEXT: [[V0]] = 0;
67 // CPP-DECLTOP-NEXT: int8_t [[V0:[^ ]*]];
72 // CPP-DECLTOP-NEXT: [[V0]] = 0;
83 // CPP-DEFAULT-NEXT: return [[V0]];
87 // CPP-DECLTOP-NEXT: [[V0]] = 0;
88 // CPP-DECLTOP-NEXT: return [[V0]];
102 // CPP-DECLTOP: int32_t [[V0:[^ ]*]];
104 // CPP-DECLTOP: [[V0]] = 0;
113 // CPP-DEFAULT-NEXT: return [[V0]];
[all …]
H A Dcast.mlir4 // CHECK-NEXT: uint32_t [[V1:[^ ]*]] = (uint32_t) [[V0:[^ ]*]]
7 // CHECK-NEXT: int64_t [[V4:[^ ]*]] = (int64_t) [[V0:[^ ]*]]
9 // CHECK-NEXT: int64_t [[V5:[^ ]*]] = (uint64_t) [[V0:[^ ]*]]
12 // CHECK-NEXT: float [[V4:[^ ]*]] = (float) [[V0:[^ ]*]]
14 // CHECK-NEXT: double [[V5:[^ ]*]] = (double) [[V0:[^ ]*]]
17 // CHECK-NEXT: bool [[V6:[^ ]*]] = (bool) [[V0:[^ ]*]]
20 // CHECK-NEXT: mytype [[V7:[^ ]*]] = (mytype) [[V0:[^ ]*]]
27 // CHECK-NEXT: int32_t* [[V1:[^ ]*]] = (int32_t*) [[V0:[^ ]*]]
H A Dif.mlir10 // CPP-DEFAULT: void test_if(bool [[V0:[^ ]*]], float [[V1:[^ ]*]]) {
11 // CPP-DEFAULT-NEXT: if ([[V0]]) {
17 // CPP-DECLTOP: void test_if(bool [[V0:[^ ]*]], float [[V1:[^ ]*]]) {
19 // CPP-DECLTOP-NEXT: if ([[V0]]) {
34 // CPP-DEFAULT: void test_if_else(bool [[V0:[^ ]*]], float [[V1:[^ ]*]]) {
35 // CPP-DEFAULT-NEXT: if ([[V0]]) {
44 // CPP-DECLTOP: void test_if_else(bool [[V0:[^ ]*]], float [[V1:[^ ]*]]) {
47 // CPP-DECLTOP-NEXT: if ([[V0]]) {
70 // CPP-DEFAULT: void test_if_yield(bool [[V0:[^ ]*]], float [[V1:[^ ]*]]) {
74 // CPP-DEFAULT-NEXT: if ([[V0]]) {
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-readobj/ELF/
H A Dbb-addr-map.test162 # V0: BBAddrMap [
163 # V0-NEXT: Function {
165 # V0-NEXT: Name: foo
166 # V0-NEXT: BB entries [
167 # V0-NEXT: {
172 # V0-NEXT: IsEHPad:
174 # V0-NEXT: }
175 # V0-NEXT: {
182 # V0-NEXT: }
183 # V0-NEXT: ]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/autohvx/
H A Dwiden-ext.ll6 ; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
7 ; CHECK: v[[V1:[0-9]+]]:[[V2:[0-9]+]].h = vunpack(v[[V0]].b)
19 ; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
20 ; CHECK: v[[V1:[0-9]+]]:[[V2:[0-9]+]].h = vunpack(v[[V0]].b)
32 ; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
33 ; CHECK: v[[V1:[0-9]+]]:[[V2:[0-9]+]].h = vunpack(v[[V0]].b)
44 ; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
59 ; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
72 ; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
85 ; CHECK-DAG: v[[V0:[0-9]+]].w = vinsert(r[[R0]])
[all …]
H A Dwiden-trunc.ll8 ; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
9 ; CHECK: v[[V1:[0-9]+]].b = vdeal(v[[V0]].b)
22 ; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
36 ; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
37 ; CHECK: v[[V1:[0-9]+]].b = vdeal(v[[V0]].b)
49 ; CHECK-DAG: v[[V0:[0-9]+]] = vmem(r0+#0)
65 ; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
66 ; CHECK: v[[V1:[0-9]+]].h = vdeal(v[[V0]].h)
79 ; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
80 ; CHECK: v[[V1:[0-9]+]].h = vdeal(v[[V0]].h)
[all …]
/llvm-project-15.0.7/llvm/test/tools/obj2yaml/ELF/
H A Dbb-addr-map.yaml171 # V0: --- !ELF
172 # V0-NEXT: FileHeader:
173 # V0-NEXT: Class: ELFCLASS64
174 # V0-NEXT: Data: ELFDATA2LSB
175 # V0-NEXT: Type: ET_EXEC
176 # V0-NEXT: Sections:
177 # V0-NEXT: - Name: .llvm_bb_addr_map
179 # V0-NEXT: Entries:
180 # V0-NEXT: - Version: 0
181 # V0-NEXT: Address: 0x1111
[all …]
/llvm-project-15.0.7/clang/test/CodeGenObjC/
H A Dweak-in-c-struct.m30 // ARM64: %[[V1]] = bitcast i8** %[[V0]] to i8*
40 // ARM64: %[[V1:.*]] = bitcast i8** %[[V0]] to i8*
64 // ARM64: %[[V2:.*]] = bitcast i8** %[[V0]] to i32*
68 // ARM64: %[[V5:.*]] = bitcast i8** %[[V0]] to i8*
90 // ARM64: %[[V2:.*]] = bitcast i8** %[[V0]] to i32*
94 // ARM64: %[[V5:.*]] = bitcast i8** %[[V0]] to i8*
118 // ARM64: %[[V2:.*]] = bitcast i8** %[[V0]] to i32*
122 // ARM64: %[[V5:.*]] = bitcast i8** %[[V0]] to i8*
145 // ARM64: %[[V2:.*]] = bitcast i8** %[[V0]] to i32*
149 // ARM64: %[[V5:.*]] = bitcast i8** %[[V0]] to i8*
[all …]
H A Dnontrivial-c-struct-within-struct-name.m28 // CHECK: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8
29 // CHECK: call void @__destructor_8_S_s0(i8** %[[V0]])
35 // CHECK: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8
36 // CHECK: call void @__destructor_8_s0(i8** %[[V0]])
42 // CHECK: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8
43 // CHECK: call void @llvm.objc.storeStrong(i8** %[[V0]], i8* null)
H A Dstrong-in-c-struct.m127 // CHECK: %[[V1:.*]] = bitcast i8** %[[V0]] to i8*
138 // CHECK: %[[V1:.*]] = bitcast i8** %[[V0]] to i8*
150 // CHECK: %[[V1:.*]] = bitcast i8** %[[V0]] to i8*
160 // CHECK: %[[V1:.*]] = bitcast i8** %[[V0]] to i8*
190 // CHECK: %[[V2:.*]] = bitcast i8** %[[V0]] to i8*
199 // CHECK: %[[V10:.*]] = bitcast i8** %[[V0]] to i8*
218 // CHECK: %[[V2:.*]] = bitcast i8** %[[V0]] to i8*
221 // CHECK: %[[V4:.*]] = bitcast i8** %[[V0]] to i8*
243 // CHECK: %[[V2:.*]] = bitcast i8** %[[V0]] to i8*
275 // CHECK: %[[V2:.*]] = bitcast i8** %[[V0]] to i8*
[all …]
/llvm-project-15.0.7/mlir/test/Transforms/
H A Dcontrol-flow-sink-test.mlir9 // CHECK-NEXT: %[[V0:.*]] = "test.sink_me"() {was_sunk = 0 : i32}
10 // CHECK-NEXT: "test.use"(%[[V0]])
23 // CHECK-NEXT: %[[V0:.*]] = "test.sink_me"() {first, was_sunk = 0 : i32}
24 // CHECK-NEXT: "test.use"(%[[V0]])
39 // CHECK-NEXT: %[[V0:.*]] = "test.sink_me"
40 // CHECK-NEXT: "test.use"(%[[V0]], %[[V1]])
H A Dcontrol-flow-sink.mlir8 // CHECK-NEXT: %[[V0:.*]] = arith.subi %[[ARG2]], %[[ARG1]]
16 // CHECK-NEXT: %[[V3:.*]] = arith.addi %[[V0]], %[[V2]]
21 // CHECK-NEXT: %[[V3:.*]] = arith.addi %[[V2]], %[[V0]]
70 // CHECK-NEXT: return %[[V0]]
116 // CHECK-NEXT: return %[[V0]]
141 // CHECK-NEXT: %[[V0:.*]] = arith.addi %[[ARG1]], %[[ARG2]]
143 // CHECK-NEXT: %[[V3:.*]] = arith.addi %[[V0]], %[[ARG2]]
150 // CHECK-NEXT: %[[V2:.*]] = arith.addi %[[V0]], %[[V1]]
191 // CHECK-NEXT: return %[[V0]]
222 // CHECK-NEXT: %[[V0:.*]] = "test.any_cond"() ({
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsMachineFunction.cpp83 Register V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg() local
94 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0) in initGlobalBaseReg()
96 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0) in initGlobalBaseReg()
108 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) in initGlobalBaseReg()
110 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0) in initGlobalBaseReg()
123 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) in initGlobalBaseReg()
125 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9); in initGlobalBaseReg()
150 MF.getRegInfo().addLiveIn(Mips::V0); in initGlobalBaseReg()
151 MBB.addLiveIn(Mips::V0); in initGlobalBaseReg()
153 .addReg(Mips::V0).addReg(Mips::T9); in initGlobalBaseReg()
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dremark_extract_broadcast.ll29 %V0 = extractelement <8 x i16> %LD, i32 0
48 %A0 = add i16 %V0, %V0
50 %A2 = add i16 %V2, %V0
51 %A3 = add i16 %V3, %V0
52 %A4 = add i16 %V4, %V0
53 %A5 = add i16 %V5, %V0
54 %A6 = add i16 %V6, %V0
55 %A7 = add i16 %V7, %V0
/llvm-project-15.0.7/clang/test/CodeGen/
H A Dvector.cpp8 int4 test1(uint4 V0) { in test1() argument
11 int4 V = !V0; in test1()
16 int4 test2(float4 V0, float4 V1) { in test2() argument
19 int4 V = !V0; in test2()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVVLPatterns.td331 (mask_type V0),
355 (mask_type V0),
425 (mask_type V0),
449 (fvti.Mask V0),
597 (fvti.Mask V0),
609 (ivti.Mask V0),
622 (fvti.Mask V0),
635 (ivti.Mask V0),
648 (fwti.Mask V0),
661 (iwti.Mask V0),
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/SCF/
H A Dcontrol-flow-sink.mlir5 // CHECK: %[[V0:.*]] = scf.if %[[ARG0]]
11 // CHECK: return %[[V0]]
30 // CHECK: %[[V0:.*]] = arith.addi %[[ARG1]], %[[ARG1]]
31 // CHECK: call @consume(%[[V0]])
49 // CHECK: %[[V0:.*]] = arith.addi %[[ARG1]], %[[ARG1]]
50 // CHECK: call @consume(%[[V0]])
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/
H A Dfold-two-entry-phi-node-with-one-block-profmd.ll12 ; CHECK-NEXT: [[V0:%.*]] = add i32 [[C:%.*]], [[D:%.*]]
13 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i32 [[V0]], i32 0
37 ; CHECK-NEXT: [[V0:%.*]] = add i32 [[C:%.*]], [[D:%.*]]
38 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i32 [[V0]], i32 0, !prof [[PROF0:![0-9]+]]
64 ; CHECK-NEXT: [[V0:%.*]] = add i32 [[C:%.*]], [[D:%.*]]
67 ; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[V0]], [[COND_TRUE]] ], [ 0, [[ENTRY:%.*]] ]
91 ; CHECK-NEXT: [[V0:%.*]] = add i32 [[C:%.*]], [[D:%.*]]
116 ; CHECK-NEXT: [[V0:%.*]] = add i32 [[C:%.*]], [[D:%.*]]
117 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i32 [[V0]], i32 0, !unpredictable !2
141 ; CHECK-NEXT: [[V0:%.*]] = add i32 [[C:%.*]], [[D:%.*]]
[all …]
H A Dfold-two-entry-phi-node-with-two-blocks-profmd.ll12 ; CHECK-NEXT: [[V0:%.*]] = add i32 [[C:%.*]], [[D:%.*]]
14 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i32 [[V0]], i32 [[V1]]
44 ; CHECK-NEXT: [[V0:%.*]] = add i32 [[C:%.*]], [[D:%.*]]
50 ; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[V0]], [[COND_TRUE]] ], [ [[V1]], [[COND_FALSE]] ]
78 ; CHECK-NEXT: [[V0:%.*]] = add i32 [[C:%.*]], [[D:%.*]]
110 ; CHECK-NEXT: [[V0:%.*]] = add i32 [[C:%.*]], [[D:%.*]]
144 ; CHECK-NEXT: [[V0:%.*]] = add i32 [[C:%.*]], [[D:%.*]]
146 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i32 [[V1]], i32 [[V0]], !prof [[PROF1]]
174 ; CHECK-NEXT: [[V0:%.*]] = add i32 [[C:%.*]], [[D:%.*]]
204 ; CHECK-NEXT: [[V0:%.*]] = add i32 [[C:%.*]], [[D:%.*]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Daarch64-minmaxv.ll138 ; CHECK: umax [[V0:v[0-9]+]].8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
139 ; CHECK: umaxv {{h[0-9]+}}, [[V0]]
152 ; CHECK-NEXT: umaxv {{s[0-9]+}}, [[V0]]
162 ; CHECK: umin [[V0:v[0-9]+]].8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
163 ; CHECK: uminv {{h[0-9]+}}, [[V0]]
176 ; CHECK-NEXT: uminv {{s[0-9]+}}, [[V0]]
186 ; CHECK: smax [[V0:v[0-9]+]].8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
187 ; CHECK: smaxv {{h[0-9]+}}, [[V0]]
200 ; CHECK-NEXT: smaxv {{s[0-9]+}}, [[V0]]
211 ; CHECK: sminv {{h[0-9]+}}, [[V0]]
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonVectorPrint.cpp74 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) || in isVecReg()
81 if (R >= Hexagon::V0 && R <= Hexagon::V31) { in getStringReg()
86 return S[R-Hexagon::V0]; in getStringReg()
183 if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) { in runOnMachineFunction()
184 LLVM_DEBUG(dbgs() << "adding dump for V" << Reg - Hexagon::V0 << '\n'); in runOnMachineFunction()
188 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1, in runOnMachineFunction()
190 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2, in runOnMachineFunction()

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