Searched refs:UZP1 (Results 1 – 9 of 9) sorted by relevance
| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | sve-uunpklo-load-uzp1-store-combine.ll | 99 ; UZP1 + Store
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| H A D | sve-intrinsics-perm-select.ll | 1628 ; UZP1
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 183 UZP1, enumerator
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| H A D | AArch64ISelLowering.cpp | 2128 MAKE_CASE(AArch64ISD::UZP1) in getTargetNodeName() 4577 return DAG.getNode(AArch64ISD::UZP1, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN() 11690 return DAG.getNode(AArch64ISD::UZP1, DL, VT, NewLo, Hi); in LowerINSERT_SUBVECTOR() 11695 return DAG.getNode(AArch64ISD::UZP1, DL, VT, Lo, NewHi); in LowerINSERT_SUBVECTOR() 11828 return DAG.getNode(AArch64ISD::UZP1, dl, VT, ResultLo, ResultHi); in LowerDIV() 17307 if (Op0.getOperand(0).getOpcode() == AArch64ISD::UZP1) { in performUzpCombine() 17309 return DAG.getNode(AArch64ISD::UZP1, DL, ResVT, X, Op1); in performUzpCombine() 17315 if (Op1.getOperand(0).getOpcode() == AArch64ISD::UZP1) { in performUzpCombine() 17317 return DAG.getNode(AArch64ISD::UZP1, DL, ResVT, Op0, Z); in performUzpCombine() 17614 if (Value.getOpcode() == AArch64ISD::UZP1 && Value->hasOneUse() && in performMSTORECombine() [all …]
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| H A D | AArch64SchedKryoDetails.td | 2329 (instregex "((TRN1|TRN2|ZIP1|UZP1|UZP2)v2i64|ZIP2(v2i64|v4i32|v8i16|v16i8))")>; 2359 (instregex "(UZP1|UZP2)(v4i32|v8i16|v16i8)")>; 2365 (instregex "(UZP1|UZP2|ZIP1|ZIP2)(v2i32|v4i16|v8i8)")>;
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| H A D | AArch64SchedFalkorDetails.td | 920 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(TRN1|TRN2|ZIP1|UZP1|UZP2|ZIP2|XTN)(v2i32|v2i64|…
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| H A D | AArch64SchedThunderX3T110.td | 1642 (instregex "^UZP1", "^UZP2", "^ZIP1", "^ZIP2")>;
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| H A D | AArch64SchedA64FX.td | 1944 (instregex "^UZP1", "^UZP2", "^ZIP1", "^ZIP2")>;
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| H A D | AArch64InstrInfo.td | 592 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>; 5415 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;
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