2128     MAKE_CASE(AArch64ISD::UZP1)  in getTargetNodeName()
4577     return DAG.getNode(AArch64ISD::UZP1, dl, Op.getValueType(),  in LowerINTRINSIC_WO_CHAIN()
10202     return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,  in GeneratePerfectShuffle()
10547     unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;  in LowerVECTOR_SHUFFLE()
10560     unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;  in LowerVECTOR_SHUFFLE()
11300         return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), LHS,  in LowerBUILD_VECTOR()
11690         return DAG.getNode(AArch64ISD::UZP1, DL, VT, NewLo, Hi);  in LowerINSERT_SUBVECTOR()
11695         return DAG.getNode(AArch64ISD::UZP1, DL, VT, Lo, NewHi);  in LowerINSERT_SUBVECTOR()
11724       Narrow = DAG.getNode(AArch64ISD::UZP1, DL, NarrowVT, Vec1, HiVec0);  in LowerINSERT_SUBVECTOR()
11729       Narrow = DAG.getNode(AArch64ISD::UZP1, DL, NarrowVT, LoVec0, Vec1);  in LowerINSERT_SUBVECTOR()
11828   return DAG.getNode(AArch64ISD::UZP1, dl, VT, ResultLo, ResultHi);  in LowerDIV()
17307     if (Op0.getOperand(0).getOpcode() == AArch64ISD::UZP1) {  in performUzpCombine()
17309       return DAG.getNode(AArch64ISD::UZP1, DL, ResVT, X, Op1);  in performUzpCombine()
17315     if (Op1.getOperand(0).getOpcode() == AArch64ISD::UZP1) {  in performUzpCombine()
17317       return DAG.getNode(AArch64ISD::UZP1, DL, ResVT, Op0, Z);  in performUzpCombine()
17614   if (Value.getOpcode() == AArch64ISD::UZP1 && Value->hasOneUse() &&  in performMSTORECombine()
19591   case AArch64ISD::UZP1:  in PerformDAGCombine()
21195   SDValue ScalableResult = DAG.getNode(AArch64ISD::UZP1, dl, ContainerVT,  in LowerFixedLengthVectorIntDivideToSVE()
21253     Val = DAG.getNode(AArch64ISD::UZP1, DL, MVT::nxv4i32, Val, Val);  in LowerFixedLengthVectorTruncateToSVE()
21259     Val = DAG.getNode(AArch64ISD::UZP1, DL, MVT::nxv8i16, Val, Val);  in LowerFixedLengthVectorTruncateToSVE()
21265     Val = DAG.getNode(AArch64ISD::UZP1, DL, MVT::nxv16i8, Val, Val);  in LowerFixedLengthVectorTruncateToSVE()
21835       unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;  in LowerFixedLengthVECTOR_SHUFFLEToSVE()
21845       unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;  in LowerFixedLengthVECTOR_SHUFFLEToSVE()