| /llvm-project-15.0.7/llvm/test/CodeGen/ARM/ |
| H A D | movc-peephole.mir | 28 …; CHECK-NEXT: [[UXTH:%[0-9]+]]:gprnopc = UXTH killed [[ORRrsi1]], 0, 0 /* CC::eq */, $cpsr, implic…
29 ; CHECK-NEXT: $r0 = COPY killed [[UXTH]]
37 %6:gprnopc = UXTH killed %5:gprnopc, 0, 14, $noreg
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| H A D | misched-int-basic.mir | 41 # CHECK: SU(4): %4:gprnopc = UXTH %3:gprnopc, 0, 14, $noreg
116 %4 = UXTH %3, 0, 14, $noreg
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 42 UXTH, enumerator
62 case AArch64_AM::UXTH: return "uxth"; in getShiftExtendName()
129 case 1: return AArch64_AM::UXTH; in getExtendType()
156 case AArch64_AM::UXTH: return 1; break; in getExtendEncoding()
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| /llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/ |
| H A D | thumb1.txt | 521 # UXTB/UXTH
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| H A D | basic-arm-instructions.txt | 2506 # UXTH
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| H A D | thumb2.txt | 2672 # UXTH
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| /llvm-project-15.0.7/llvm/test/CodeGen/ARM/GlobalISel/ |
| H A D | arm-instruction-select.mir | 171 ; CHECK: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY1]], 0, 14 /* CC::al */, $noreg
172 ; CHECK: $r0 = COPY [[UXTH]]
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedPredicates.td | 19 def CheckExtUXTH : CheckImmOperand_s<3, "AArch64_AM::UXTH">;
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| H A D | AArch64ExpandPseudoInsts.cpp | 1181 AArch64_AM::getArithExtendImm(AArch64_AM::UXTH, 0), in expandMI()
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| H A D | AArch64ISelDAGToDAG.cpp | 655 return AArch64_AM::UXTH; in getExtendTypeForNode()
673 return !IsLoadStore ? AArch64_AM::UXTH : AArch64_AM::InvalidShiftExtend; in getExtendTypeForNode()
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| H A D | AArch64InstrInfo.cpp | 902 case AArch64_AM::UXTH: in isFalkorShiftExtFast()
936 case AArch64_AM::UXTH: in isFalkorShiftExtFast()
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| H A D | AArch64FastISel.cpp | 1154 ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH; in emitAddSub()
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | sve-intrinsics-conversion.ll | 121 ; UXTH
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 558 UXTH, enumerator
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| /llvm-project-15.0.7/llvm/test/MC/ARM/ |
| H A D | basic-thumb-instructions.s | 656 @ UXTB/UXTH
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 301 STORE_OPCODE(ZEXT16, UXTH); in OpcodeCache()
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| H A D | ARMFastISel.cpp | 2663 /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } } in ARMEmitIntExt()
2903 { { ARM::UXTH, ARM::t2UXTH }, 0, 1, MVT::i16 },
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| H A D | ARMScheduleR52.td | 215 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
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| H A D | ARMScheduleSwift.td | 161 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
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| H A D | ARMScheduleA57.td | 361 // Sign/zero extend, normal: SXTB, SXTH, UXTB, UXTH
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| H A D | ARMInstrThumb.td | 1781 // restrict the register class for the UXTB/UXTH ops used in the expansion.
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| H A D | ARMInstrInfo.td | 3752 def UXTH : AI_ext_rrot<0b01101111,
6119 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
6263 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
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| H A D | ARMExpandPseudoInsts.cpp | 3060 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH, ARM::UXTH, in ExpandMI()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1380 ET == AArch64_AM::UXTH || ET == AArch64_AM::SXTH || in isExtend()
1393 ET == AArch64_AM::UXTH || ET == AArch64_AM::SXTH || in isExtend64()
3204 .Case("uxth", AArch64_AM::UXTH) in tryParseOptionalShiftExtend()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 6588 return IsLoadStore ? AArch64_AM::InvalidShiftExtend : AArch64_AM::UXTH; in getExtendTypeForInst()
6611 return !IsLoadStore ? AArch64_AM::UXTH : AArch64_AM::InvalidShiftExtend; in getExtendTypeForInst()
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