Searched refs:TruncMask (Results 1 – 6 of 6) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | MVELaneInterleavingPass.cpp | 319 SmallVector<int, 16> TruncMask; in tryInterleave() local
330 TruncMask.push_back(Base + i); in tryInterleave()
331 TruncMask.push_back(Base + i + BaseElts / 2); in tryInterleave()
360 Value *Shuf = Builder.CreateShuffleVector(I, TruncMask); in tryInterleave()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCodeGenPrepare.cpp | 1005 ConstantInt *TruncMask in expandDivRem24Impl() local
1007 Res = Builder.CreateAnd(Res, TruncMask); in expandDivRem24Impl()
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| H A D | AMDGPUISelLowering.cpp | 1675 SDValue TruncMask = DAG.getConstant((UINT64_C(1) << DivBits) - 1, DL, VT); in LowerDIVREM24() local
1676 Div = DAG.getNode(ISD::AND, DL, VT, Div, TruncMask); in LowerDIVREM24()
1677 Rem = DAG.getNode(ISD::AND, DL, VT, Rem, TruncMask); in LowerDIVREM24()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 2359 APInt TruncMask = DemandedBits.zext(OperandBitWidth); in SimplifyDemandedBits() local
2360 if (SimplifyDemandedBits(Src, TruncMask, DemandedElts, Known, TLO, in SimplifyDemandedBits()
2367 Src, TruncMask, DemandedElts, TLO.DAG, Depth + 1)) in SimplifyDemandedBits()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 13664 uint64_t TruncMask = ShiftLHS.getConstantOperandVal(1); in isDesirableToCommuteWithShift() local
13665 if (isMask_64(TruncMask) && in isDesirableToCommuteWithShift()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 41629 APInt TruncMask = OriginalDemandedBits.zext(SrcVT.getScalarSizeInBits()); in SimplifyDemandedBitsForTargetNode() local
41631 if (SimplifyDemandedBits(Src, TruncMask, DemandedElts, KnownOp, TLO, Depth + 1)) in SimplifyDemandedBitsForTargetNode()
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