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Searched refs:Tile (Results 1 – 25 of 28) sorted by relevance

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/llvm-project-15.0.7/clang/test/OpenMP/
H A Dtile_ast_print.cpp144 template<typename T, T Step, T Tile>
150 #pragma omp tile sizes(Tile) in foo6()
167 template <int Tile>
173 #pragma omp tile sizes(Tile) in foo7()
H A Dtile_codegen.cpp75 template<typename T, T Step, T Tile>
77 #pragma omp tile sizes(Tile) in foo7()
/llvm-project-15.0.7/mlir/include/mlir/Dialect/AMX/
H A DAMX.td80 // Tile reset.
108 // Tile memory operations.
173 // Tile arithmetic operations.
257 // Tile reset. Parameters define the tile size.
264 // Tile memory operations. Parameters define the tile size,
278 // Tile multiplication operations (series of dot products). Parameters
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A DO0-pipeline.ll44 ; CHECK-NEXT: Fast Tile Register Preconfigure
48 ; CHECK-NEXT: Fast Tile Register Configure
49 ; CHECK-NEXT: X86 Lower Tile Copy
H A Dopt-pipeline.ll126 ; CHECK-NEXT: Tile Register Pre-configure
148 ; CHECK-NEXT: Tile Register Configure
155 ; CHECK-NEXT: X86 Lower Tile Copy
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86LowerAMXIntrinsics.cpp79 Value *Ptr, Value *Stride, Value *Tile);
151 Value *Col, Value *Ptr, Value *Stride, Value *Tile) { in createTileLoadStoreLoops() argument
221 auto *BitCast = cast<BitCastInst>(Tile); in createTileLoadStoreLoops()
517 Value *M, *N, *Ptr, *Stride, *Tile; in lowerTileLoadStore() local
525 m_Value(Stride), m_Value(Tile))); in lowerTileLoadStore()
538 IsTileLoad ? nullptr : Tile); in lowerTileLoadStore()
H A DX86LowerAMXType.cpp262 Value *Tile = Bitcast->getOperand(0); in combineBitcastStore() local
263 auto *II = cast<IntrinsicInst>(Tile); in combineBitcastStore()
274 std::array<Value *, 5> Args = {Row, Col, I8Ptr, Stride, Tile}; in combineBitcastStore()
920 Value *Tile = Cast->getOperand(0); in combineCastStore() local
923 if (!isAMXIntrinsic(Tile)) in combineCastStore()
925 auto *II = cast<IntrinsicInst>(Tile); in combineCastStore()
936 std::array<Value *, 5> Args = {Row, Col, I8Ptr, Stride, Tile}; in combineCastStore()
H A DX86RegisterInfo.td268 // Tile config registers.
271 // Tile "registers".
/llvm-project-15.0.7/mlir/include/mlir/Dialect/Linalg/Transforms/
H A DCodegenStrategy.h51 struct Tile : public Transformation { struct
52 Tile(StringRef name, linalg::LinalgTilingOptions options,
213 std::make_unique<Tile>(opName, options, f));
/llvm-project-15.0.7/flang/lib/Semantics/
H A Dcanonicalize-acc.cpp61 std::get_if<parser::AccClause::Tile>(&clause.u)) { in CheckTileClauseRestriction()
102 std::holds_alternative<parser::AccClause::Tile>(clause.u)) { in CheckDoConcurrentClauseRestriction()
H A Dcheck-acc-structure.cpp344 CHECK_SIMPLE_CLAUSE(Tile, ACCC_tile) in CHECK_REQ_SCALAR_INT_CONSTANT_CLAUSE()
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dtransform-tile-and-fuse.mlir51 // Tile the root.
112 // Tile the root.
/llvm-project-15.0.7/llvm/docs/Proposals/
H A DVectorizationPlan.rst109 Hierarchical CFG data structure is similar to the Tile Tree [5]_, where
110 cross-Tile edges are lifted to connect Tiles instead of the original
111 basic-blocks as in Sharir [6]_, promoting the Tile encapsulation. The terms
112 Region and Block are used rather than Tile [5]_ to avoid confusion with loop
/llvm-project-15.0.7/mlir/include/mlir/Dialect/SCF/Transforms/
H A DPasses.td73 let summary = "Tile parallel loops";
/llvm-project-15.0.7/mlir/include/mlir/Dialect/Linalg/
H A DPasses.td116 let summary = "Tile operations in the linalg dialect";
125 ListOption<"tileSizes", "tile-sizes", "int64_t", "Tile sizes">,
/llvm-project-15.0.7/llvm/unittests/Frontend/
H A DOpenMPIRBuilderTest.cpp1446 CanonicalLoopInfo *Tile = GenLoops[1]; in TEST_F() local
1450 Floor->getBody(), Tile->getPreheader(), Tile->getHeader(), in TEST_F()
1451 Tile->getCond(), Tile->getBody(), BodyCode, in TEST_F()
1452 Tile->getLatch(), Tile->getExit(), Tile->getAfter(), in TEST_F()
1461 EXPECT_EQ(cast<Instruction>(Shift)->getParent(), Tile->getBody()); in TEST_F()
1462 EXPECT_EQ(Shift->getOperand(1), Tile->getIndVar()); in TEST_F()
1464 EXPECT_EQ(cast<Instruction>(Scale)->getParent(), Tile->getBody()); in TEST_F()
/llvm-project-15.0.7/mlir/include/mlir/Dialect/Linalg/TransformOps/
H A DLinalgTransformOps.td612 Tile sizes may be known at transformation time, in which case they are
668 Tile a TilingInterface op to a tiled `scf.foreach_thread`. Tiling is
/llvm-project-15.0.7/mlir/include/mlir/Dialect/Affine/
H A DPasses.td185 let summary = "Tile affine loop nests";
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td1252 // * Tile vectors:
1279 # "MatrixKind::Tile" # ", "
1294 // Tile vectors (horizontal and vertical)
H A DSMEInstrFormats.td193 // SME Add Vector to Tile
/llvm-project-15.0.7/flang/lib/Lower/
H A DOpenACC.cpp266 std::get_if<Fortran::parser::AccClause::Tile>(&clause.u)) { in createLoopOp()
/llvm-project-15.0.7/openmp/runtime/src/i18n/
H A Den_US.txt105 Tile "tile"
/llvm-project-15.0.7/mlir/docs/Dialects/
H A DVector.md245 first-class n-D values in MLIR. The alternative name Tile has been proposed,
/llvm-project-15.0.7/mlir/include/mlir/Dialect/Tosa/IR/
H A DTosaOps.td1511 let summary = "Tile operator";
/llvm-project-15.0.7/mlir/docs/Dialects/Linalg/
H A D_index.md30 1. Tiled Producer-Consumer Fusion with Parametric Tile-And-Fuse.

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