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Searched refs:TempRegID (Results 1 – 9 of 9) sorted by relevance

/llvm-project-15.0.7/llvm/test/TableGen/
H A DGlobalISelEmitterSubreg.td55 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
74 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
75 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
108 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
109 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
133 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
149 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
168 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
169 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
181 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
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H A DGlobalISelEmitterRegSequence.td42 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
43 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
45 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
49 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
54 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
56 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
69 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
70 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
72 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
H A DGlobalISelEmitter-nested-subregs.td41 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
44 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
47 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
48 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
56 // CHECK-NEXT: GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, MyTarget::lo…
H A DGlobalISelEmitter-input-discard.td19 // GISEL-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21 // GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
25 // GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
H A DGlobalISelEmitter-output-discard.td16 // GISEL-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
19 // GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|R…
H A DDefaultOpsGlobalISel.td80 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
82 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
89 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
H A DGlobalISelEmitter.td288 // R19C-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
290 // R19C-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
301 // R19C-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DGlobalISelEmitter.cpp2849 unsigned TempRegID; member in __anoncee47b830111::TempRegRenderer
2858 : OperandRenderer(OR_Register), InsnID(InsnID), TempRegID(TempRegID), in TempRegRenderer()
3242 unsigned TempRegID; member in __anoncee47b830111::MakeTempRegisterAction
3246 : Ty(Ty), TempRegID(TempRegID) { in MakeTempRegisterAction()
4510 InsertPt, *OpTy, TempRegID); in importExplicitUseRenderer()
4514 ++InsertPt, Rule, DstChild, TempRegID); in importExplicitUseRenderer()
4625 unsigned TempRegID) { in createAndImportSubInstructionRenderer() argument
4791 unsigned TempRegID = M.allocateTempRegID(); in importExplicitDefRenderers() local
4826 unsigned TempRegID = M.allocateTempRegID(); in importExplicitUseRenderers() local
4828 InsertPt, *ExtractSrcTy, TempRegID); in importExplicitUseRenderers()
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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DInstructionSelectorImpl.h959 int64_t TempRegID = MatchTable[CurrentIdx++]; in executeMatchTable() local
967 OutMIs[InsnID].addReg(State.TempRegisters[TempRegID], TempRegFlags, SubReg); in executeMatchTable()
970 << InsnID << "], TempRegisters[" << TempRegID in executeMatchTable()
1142 int64_t TempRegID = MatchTable[CurrentIdx++]; in executeMatchTable() local
1145 State.TempRegisters[TempRegID] = in executeMatchTable()
1148 dbgs() << CurrentIdx << ": TempRegs[" << TempRegID in executeMatchTable()