Home
last modified time | relevance | path

Searched refs:TargetSubtargetInfo (Results 1 – 25 of 102) sorted by relevance

12345

/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetSubtargetInfo.cpp17 TargetSubtargetInfo::TargetSubtargetInfo( in TargetSubtargetInfo() function in TargetSubtargetInfo
25 TargetSubtargetInfo::~TargetSubtargetInfo() = default;
27 bool TargetSubtargetInfo::enableAtomicExpand() const { in enableAtomicExpand()
31 bool TargetSubtargetInfo::enableIndirectBrExpand() const { in enableIndirectBrExpand()
35 bool TargetSubtargetInfo::enableMachineScheduler() const { in enableMachineScheduler()
39 bool TargetSubtargetInfo::enableJoinGlobalCopies() const { in enableJoinGlobalCopies()
43 bool TargetSubtargetInfo::enableRALocalReassignment( in enableRALocalReassignment()
48 bool TargetSubtargetInfo::enablePostRAScheduler() const { in enablePostRAScheduler()
52 bool TargetSubtargetInfo::enablePostRAMachineScheduler() const { in enablePostRAMachineScheduler()
56 bool TargetSubtargetInfo::useAA() const { in useAA()
[all …]
H A DPostRASchedulerList.cpp105 TargetSubtargetInfo::AntiDepBreakMode &Mode,
146 TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
205 TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, in SchedulePostRATDList()
216 assert((AntiDepMode == TargetSubtargetInfo::ANTIDEP_NONE || in SchedulePostRATDList()
263 const TargetSubtargetInfo &ST, in enablePostRAScheduler()
265 TargetSubtargetInfo::AntiDepBreakMode &Mode, in enablePostRAScheduler()
289 TargetSubtargetInfo::AntiDepBreakMode AntiDepMode = in runOnMachineFunction()
290 TargetSubtargetInfo::ANTIDEP_NONE; in runOnMachineFunction()
302 ? TargetSubtargetInfo::ANTIDEP_ALL in runOnMachineFunction()
304 ? TargetSubtargetInfo::ANTIDEP_CRITICAL in runOnMachineFunction()
[all …]
H A DRegisterUsageInfo.cpp90 = TM->getSubtarget<TargetSubtargetInfo>(*(FPRMPair->first)) in print()
H A DMachineCycleAnalysis.cpp93 const TargetSubtargetInfo &ST = MF->getSubtarget(); in isCycleInvariant()
H A DAggressiveAntiDepBreaker.h134 TargetSubtargetInfo::RegClassVector& CriticalPathRCs);
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetSubtargetInfo.h60 class TargetSubtargetInfo : public MCSubtargetInfo {
62 TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU,
76 TargetSubtargetInfo() = delete;
77 TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
78 TargetSubtargetInfo &operator=(const TargetSubtargetInfo &) = delete;
79 ~TargetSubtargetInfo() override;
H A DTargetSchedule.h35 const TargetSubtargetInfo *STI = nullptr;
56 void init(const TargetSubtargetInfo *TSInfo);
62 const TargetSubtargetInfo *getSubtargetInfo() const { return STI; } in getSubtargetInfo()
H A DMacroFusion.h25 class TargetSubtargetInfo; variable
33 const TargetSubtargetInfo &TSI,
H A DVLIWMachineScheduler.h29 class TargetSubtargetInfo; variable
50 VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM);
64 virtual DFAPacketizer *createPacketizer(const TargetSubtargetInfo &STI) const;
241 createVLIWResourceModel(const TargetSubtargetInfo &STI,
H A DAntiDepBreaker.h96 TargetSubtargetInfo::RegClassVector &CriticalPathRCs);
H A DModuloSchedule.h171 const TargetSubtargetInfo &ST;
296 const TargetSubtargetInfo &ST;
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/MIRParser/
H A DMIParser.h35 class TargetSubtargetInfo; variable
55 const TargetSubtargetInfo &Subtarget;
151 PerTargetMIParsingState(const TargetSubtargetInfo &STI) in PerTargetMIParsingState()
159 void setTarget(const TargetSubtargetInfo &NewSubtarget);
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetMachine.h46 const TargetSubtargetInfo *getSubtargetImpl() const;
47 const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override = 0;
87 const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override;
H A DAMDGPUMCInstLower.h31 const TargetSubtargetInfo &ST;
35 AMDGPUMCInstLower(MCContext &ctx, const TargetSubtargetInfo &ST,
H A DAMDGPUMacroFusion.cpp27 const TargetSubtargetInfo &TSI, in shouldScheduleAdjacent()
H A DR600TargetMachine.h39 const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override;
H A DAMDGPUTargetTransformInfo.h42 const TargetSubtargetInfo *ST;
45 const TargetSubtargetInfo *getST() const { return ST; } in getST()
/llvm-project-15.0.7/llvm/unittests/CodeGen/
H A DMFCommon.inc72 class BogusSubtarget : public TargetSubtargetInfo {
75 : TargetSubtargetInfo(Triple(""), "", "", "", {}, {}, nullptr, nullptr,
111 const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override {
131 const TargetSubtargetInfo &STI = *TM->getSubtargetImpl(*F);
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.h34 createVLIWResourceModel(const TargetSubtargetInfo &STI,
H A DHexagonMachineScheduler.cpp41 const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const { in createVLIWResourceModel()
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVTargetTransformInfo.h33 const TargetSubtargetInfo *getST() const { return ST; } in getST()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVMacroFusion.cpp54 const TargetSubtargetInfo &TSI, in shouldScheduleAdjacent()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMMacroFusion.cpp52 const TargetSubtargetInfo &TSI, in shouldScheduleAdjacent()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86MacroFusion.cpp36 const TargetSubtargetInfo &TSI, in shouldScheduleAdjacent()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetMachine.h59 class TargetSubtargetInfo; variable
133 virtual const TargetSubtargetInfo *getSubtargetImpl(const Function &) const { in getSubtargetImpl()

12345