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Searched refs:TargetRegisterInfo (Results 1 – 25 of 437) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetRegisterInfo.cpp53 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID, in TargetRegisterInfo() function in TargetRegisterInfo
67 TargetRegisterInfo::~TargetRegisterInfo() = default;
69 bool TargetRegisterInfo::shouldRegionSplitForVirtReg( in shouldRegionSplitForVirtReg()
318 const TargetRegisterClass *TargetRegisterInfo::
422 bool TargetRegisterInfo::getRegAllocationHints( in getRegAllocationHints()
465 bool TargetRegisterInfo::isCalleeSavedPhysReg( in isCalleeSavedPhysReg()
502 TargetRegisterInfo::getRegSizeInBits(Register Reg, in getRegSizeInBits()
524 bool TargetRegisterInfo::getCoveringSubRegIndexes( in getCoveringSubRegIndexes()
596 TargetRegisterInfo::lookThruCopyLike(Register SrcReg, in lookThruCopyLike()
618 Register TargetRegisterInfo::lookThruSingleUseCopyChain( in lookThruSingleUseCopyChain()
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H A DRegisterCoalescer.h23 class TargetRegisterInfo; variable
29 const TargetRegisterInfo &TRI;
60 CoalescerPair(const TargetRegisterInfo &tri) : TRI(tri) {} in CoalescerPair()
65 const TargetRegisterInfo &tri) in CoalescerPair()
H A DInterferenceCache.h30 class TargetRegisterInfo; variable
117 void revalidate(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
120 bool valid(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
124 const TargetRegisterInfo *TRI, const MachineFunction *MF);
139 const TargetRegisterInfo *TRI = nullptr;
169 const TargetRegisterInfo *tri);
H A DTargetFrameLoweringImpl.cpp53 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); in getFrameIndexReference()
72 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); in getCalleeSaves()
86 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); in determineCalleeSaves()
149 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in allocateScavengingFrameIndexesNearIncomingSP()
177 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); in getDwarfFrameBase()
H A DRegisterBank.cpp32 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const { in verify()
82 LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const { in dump()
88 const TargetRegisterInfo *TRI) const { in print()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DRegisterBank.h23 class TargetRegisterInfo; variable
65 bool verify(const TargetRegisterInfo &TRI) const;
81 void dump(const TargetRegisterInfo *TRI = nullptr) const;
89 const TargetRegisterInfo *TRI = nullptr) const;
H A DRegAllocCommon.h17 class TargetRegisterInfo; variable
19 typedef std::function<bool(const TargetRegisterInfo &TRI,
24 static inline bool allocateAllRegClasses(const TargetRegisterInfo &, in allocateAllRegClasses() argument
H A DMachineInstr.h57 class TargetRegisterInfo; variable
1344 const TargetRegisterInfo *TRI = nullptr) const {
1365 const TargetRegisterInfo *TRI = nullptr) const {
1414 const TargetRegisterInfo *TRI = nullptr) const {
1434 const TargetRegisterInfo *TRI = nullptr) {
1469 const TargetRegisterInfo *TRI) const;
1485 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1500 const TargetRegisterInfo *TRI) const;
1548 const TargetRegisterInfo &RegInfo);
1555 const TargetRegisterInfo *RegInfo,
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H A DMachineOutliner.h78 void initFromEndOfBlockToStartOfSeq(const TargetRegisterInfo &TRI) { in initFromEndOfBlockToStartOfSeq()
95 void initInSeq(const TargetRegisterInfo &TRI) { in initInSeq()
156 const TargetRegisterInfo &TRI) { in isAvailableAcrossAndOutOfSeq()
165 const TargetRegisterInfo &TRI) { in isAnyUnavailableAcrossOrOutOfSeq()
181 bool isAvailableInsideSeq(Register Reg, const TargetRegisterInfo &TRI) { in isAvailableInsideSeq()
H A DLiveRegUnits.h31 const TargetRegisterInfo *TRI = nullptr;
39 LiveRegUnits(const TargetRegisterInfo &TRI) { in LiveRegUnits()
50 const TargetRegisterInfo *TRI) { in accumulateUsedDefed()
73 void init(const TargetRegisterInfo &TRI) { in init()
H A DTargetRegisterInfo.h234 class TargetRegisterInfo : public MCRegisterInfo {
254 TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
262 virtual ~TargetRegisterInfo();
674 const TargetRegisterInfo *TRI = nullptr);
1151 const TargetRegisterInfo *TRI,
1251 BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI) in BitMaskClassIterator()
1288 Printable printReg(Register Reg, const TargetRegisterInfo *TRI = nullptr,
1300 Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
1304 Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
1309 const TargetRegisterInfo *TRI);
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64RegisterBankInfo.h23 class TargetRegisterInfo; variable
123 const TargetRegisterInfo &TRI, unsigned Depth = 0) const;
127 const TargetRegisterInfo &TRI, unsigned Depth = 0) const;
131 const TargetRegisterInfo &TRI, unsigned Depth = 0) const;
134 AArch64RegisterBankInfo(const TargetRegisterInfo &TRI);
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZFrameLowering.h58 const TargetRegisterInfo *TRI,
65 const TargetRegisterInfo *TRI) const override;
70 const TargetRegisterInfo *TRI) const override;
109 const TargetRegisterInfo *TRI,
118 const TargetRegisterInfo *TRI) const override;
124 const TargetRegisterInfo *TRI) const override;
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonBlockRanges.h29 class TargetRegisterInfo; variable
150 const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI);
153 PrintRangeMap(const RegToRangeMap &M, const TargetRegisterInfo &I) in PrintRangeMap()
160 const TargetRegisterInfo &TRI;
165 const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI);
173 const TargetRegisterInfo &TRI;
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsInstrInfo.h39 class TargetRegisterInfo; variable
140 const TargetRegisterInfo *TRI) const override { in storeRegToStackSlot()
148 const TargetRegisterInfo *TRI) const override { in loadRegFromStackSlot()
156 const TargetRegisterInfo *TRI,
163 const TargetRegisterInfo *TRI,
H A DMipsFrameLowering.cpp95 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); in hasFP()
104 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); in hasBP()
116 const TargetRegisterInfo &TRI = *STI.getRegisterInfo(); in estimateStackSize()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCFrameLowering.h46 const TargetRegisterInfo *TRI) const override;
52 const TargetRegisterInfo *TRI) const override;
64 llvm::MachineFunction &, const llvm::TargetRegisterInfo *,
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.h59 const TargetRegisterInfo *RegisterInfo) const override;
66 const TargetRegisterInfo *RegisterInfo) const override;
74 const TargetRegisterInfo *TRI) const override;
79 const TargetRegisterInfo *TRI) const;
/llvm-project-15.0.7/llvm/lib/CodeGen/AsmPrinter/
H A DDwarfExpression.h32 class TargetRegisterInfo; variable
221 virtual bool isFrameRegister(const TargetRegisterInfo &TRI,
249 bool addMachineReg(const TargetRegisterInfo &TRI, llvm::Register MachineReg,
328 bool addMachineRegExpression(const TargetRegisterInfo &TRI,
396 bool isFrameRegister(const TargetRegisterInfo &TRI,
426 bool isFrameRegister(const TargetRegisterInfo &TRI,
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.h36 const TargetRegisterInfo &getRegisterInfo() const { return RI; } in getRegisterInfo()
47 const TargetRegisterInfo *TRI) const override;
52 const TargetRegisterInfo *TRI) const override;
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.h34 const TargetRegisterInfo &getRegisterInfo() const { return RI; } in getRegisterInfo()
73 const TargetRegisterInfo *TRI) const override;
79 const TargetRegisterInfo *TRI) const override;
H A DXCoreMachineFunctionInfo.cpp46 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); in createLRSpillSlot()
64 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); in createFPSpillSlot()
77 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); in createEHSpillSlot()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h139 const TargetRegisterInfo *TRI) const override;
144 const TargetRegisterInfo *TRI) const override;
154 const TargetRegisterInfo *TRI) const;
186 const TargetRegisterInfo *TRI) const override;
191 const TargetRegisterInfo *TRI) const override;
398 const TargetRegisterInfo &TRI,
405 const TargetRegisterInfo *TRI);
407 MCCFIInstruction createDefCFA(const TargetRegisterInfo &TRI, unsigned FrameReg,
410 MCCFIInstruction createCFAOffset(const TargetRegisterInfo &MRI, unsigned Reg,
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYFrameLowering.h46 MachineFunction &MF, const TargetRegisterInfo *TRI, in assignCalleeSavedSpillSlots()
57 const TargetRegisterInfo *TRI) const override;
62 const TargetRegisterInfo *TRI) const override;
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrInfo.h247 const TargetRegisterInfo &TRI) const override;
332 const TargetRegisterInfo *TRI) const override;
339 const TargetRegisterInfo *TRI) const override;
345 const TargetRegisterInfo *TRI) const override;
370 const TargetRegisterInfo *TRI) const override;
375 const TargetRegisterInfo *TRI) const override;
482 const TargetRegisterInfo *TRI) const override;
484 const TargetRegisterInfo *TRI) const override;
486 const TargetRegisterInfo *TRI) const override;

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