| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVRedundantCopyElimination.cpp | 113 Register TargetReg = CondBr->getOperand(0).getReg(); in optimizeBlock() local
114 if (!TargetReg) in optimizeBlock()
129 TargetReg == DefReg) { in optimizeBlock()
141 if (MI->modifiesRegister(TargetReg, TRI)) in optimizeBlock()
150 CondBr->clearRegisterKills(TargetReg, TRI); in optimizeBlock()
153 if (!MBB.isLiveIn(TargetReg)) in optimizeBlock()
154 MBB.addLiveIn(TargetReg); in optimizeBlock()
158 MMI.clearRegisterKills(TargetReg, TRI); in optimizeBlock()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 186 unsigned TargetReg = Inst.getOperand(1).getReg(); in emitInstruction() local
187 emitMask(TargetReg, IndirectBranchMaskReg, STI); in emitInstruction()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86SpeculativeLoadHardening.cpp | 992 unsigned TargetReg; in tracePredStateThroughIndirectBranches() local
1023 TargetReg = TI.getOperand(0).getReg(); in tracePredStateThroughIndirectBranches()
1043 TargetAddrSSA.AddAvailableValue(&MBB, TargetReg); in tracePredStateThroughIndirectBranches()
1110 Register TargetReg = MRI->createVirtualRegister(&X86::GR64RegClass); in tracePredStateThroughIndirectBranches() local
1115 TII->get(X86::MOV64ri32), TargetReg) in tracePredStateThroughIndirectBranches()
1123 TargetReg) in tracePredStateThroughIndirectBranches()
1135 TargetAddrSSA.AddAvailableValue(Pred, TargetReg); in tracePredStateThroughIndirectBranches()
1143 Register TargetReg = TargetAddrSSA.GetValueInMiddleOfBlock(&MBB); in tracePredStateThroughIndirectBranches() local
1154 .addReg(TargetReg, RegState::Kill) in tracePredStateThroughIndirectBranches()
1173 .addReg(TargetReg, RegState::Kill) in tracePredStateThroughIndirectBranches()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIFrameLowering.cpp | 167 Register TargetReg) { in buildGitPtr() argument
172 Register TargetLo = TRI->getSubReg(TargetReg, AMDGPU::sub0); in buildGitPtr()
173 Register TargetHi = TRI->getSubReg(TargetReg, AMDGPU::sub1); in buildGitPtr()
178 .addReg(TargetReg, RegState::ImplicitDefine); in buildGitPtr()
181 BuildMI(MBB, I, DL, GetPC64, TargetReg); in buildGitPtr()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 896 Register TargetReg = I->getOperand(1).getReg(); in expandEhReturn() local
904 .addReg(TargetReg) in expandEhReturn()
907 .addReg(TargetReg) in expandEhReturn()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2988 Register TargetReg = MI.getOperand(0).getReg(); in expandVSXMemPseudo() local
2990 if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) || in expandVSXMemPseudo()
2991 (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31)) in expandVSXMemPseudo()
3075 Register TargetReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
3076 if (PPC::VSFRCRegClass.contains(TargetReg)) { in expandPostRAPseudo()
3097 Register TargetReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
3098 if (PPC::VSFRCRegClass.contains(TargetReg)) in expandPostRAPseudo()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 213 const SmallSet<Register, 2> &TargetReg,
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3599 Register TargetReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in selectBrJT() local
3604 {TargetReg, ScratchReg}, {JTAddr, Index}) in selectBrJT()
3607 MIB.buildInstr(AArch64::BR, {}, {TargetReg}); in selectBrJT()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 2834 Register TargetReg, Register InsertReg, in buildBitFieldInsert() argument
2836 LLT TargetTy = B.getMRI()->getType(TargetReg); in buildBitFieldInsert()
2850 auto MaskedOldElt = B.buildAnd(TargetTy, TargetReg, InvShiftedMask); in buildBitFieldInsert()
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