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Searched refs:TEX (Results 1 – 25 of 26) sorted by relevance

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/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/AMDGPU/
H A Dimage-d16.ll11 ; GFX7-NEXT: [[TEX_HALF:%.*]] = fptrunc float [[TEX]] to half
17 ; GFX81PLUS-NEXT: ret half [[TEX]]
29 ; GFX7-NEXT: [[TEX_2_HALF:%.*]] = fptrunc <2 x float> [[TEX]] to <2 x half>
38 ; GFX81PLUS-NEXT: [[TEX_HALF_0:%.*]] = extractelement <2 x half> [[TEX]], i64 0
39 ; GFX81PLUS-NEXT: [[TEX_HALF_1:%.*]] = extractelement <2 x half> [[TEX]], i64 1
56 ; GFX7-NEXT: [[TEX_3_HALF:%.*]] = fptrunc <3 x float> [[TEX]] to <3 x half>
67 ; GFX81PLUS-NEXT: [[TEX_HALF_0:%.*]] = extractelement <3 x half> [[TEX]], i64 0
68 ; GFX81PLUS-NEXT: [[TEX_HALF_1:%.*]] = extractelement <3 x half> [[TEX]], i64 1
69 ; GFX81PLUS-NEXT: [[TEX_HALF_2:%.*]] = extractelement <3 x half> [[TEX]], i64 2
89 ; GFX7-NEXT: [[TEX_4_HALF:%.*]] = fptrunc <4 x float> [[TEX]] to <4 x half>
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dr600.bitcast.ll10 ; EG-NEXT: TEX 0 @6
33 ; EG-NEXT: TEX 0 @6
55 ; EG-NEXT: TEX 0 @6
77 ; EG-NEXT: TEX 0 @6
99 ; EG-NEXT: TEX 0 @6
121 ; EG-NEXT: TEX 0 @6
146 ; EG-NEXT: TEX 1 @6
186 ; EG-NEXT: TEX 0 @6
H A Dkernel-args.ll47 ; EG-NEXT: TEX 0 @6
63 ; CM-NEXT: TEX 0 @6
119 ; EG-NEXT: TEX 0 @6
136 ; CM-NEXT: TEX 0 @6
194 ; EG-NEXT: TEX 0 @6
211 ; CM-NEXT: TEX 0 @6
269 ; EG-NEXT: TEX 0 @6
285 ; CM-NEXT: TEX 0 @6
341 ; EG-NEXT: TEX 0 @6
358 ; CM-NEXT: TEX 0 @6
[all …]
H A Dr600.extract-lowbits.ll52 ; EG-NEXT: TEX 0 @6
71 ; CM-NEXT: TEX 0 @6
160 ; EG-NEXT: TEX 0 @6
179 ; CM-NEXT: TEX 0 @6
268 ; EG-NEXT: TEX 0 @6
291 ; CM-NEXT: TEX 0 @6
384 ; EG-NEXT: TEX 0 @6
406 ; CM-NEXT: TEX 0 @6
H A Dvtx-fetch-branch.ll11 ; CHECK: TEX
H A Dtex-clause-antidep.ll3 ;CHECK: TEX
H A Dctpop16.ll44 ; EG-NEXT: TEX 0 @6
111 ; EG-NEXT: TEX 0 @6
193 ; EG-NEXT: TEX 0 @8
195 ; EG-NEXT: TEX 0 @10
280 ; EG-NEXT: TEX 0 @8
282 ; EG-NEXT: TEX 0 @10
369 ; EG-NEXT: TEX 0 @6
461 ; EG-NEXT: TEX 0 @6
609 ; EG-NEXT: TEX 0 @6
845 ; EG-NEXT: TEX 1 @8
[all …]
H A Dselectcc-icmp-select-float.ll10 ; CHECK-NEXT: TEX 0 @6
H A Dmul_uint24-r600.ll50 ; CM-NEXT: TEX 1 @6
73 ; EG-NEXT: TEX 1 @6
100 ; CM-NEXT: TEX 1 @6
123 ; EG-NEXT: TEX 1 @6
H A Dsrl.ll43 ; EG-NEXT: TEX 0 @6
102 ; EG-NEXT: TEX 0 @6
169 ; EG-NEXT: TEX 1 @6
230 ; EG-NEXT: TEX 0 @6
313 ; EG-NEXT: TEX 3 @6
451 ; EG-NEXT: TEX 0 @6
H A Dctlz_zero_undef.ll109 ; EG-NEXT: TEX 0 @6
186 ; EG-NEXT: TEX 0 @6
269 ; EG-NEXT: TEX 0 @6
351 ; EG-NEXT: TEX 0 @6
576 ; EG-NEXT: TEX 0 @6
668 ; EG-NEXT: TEX 0 @6
754 ; EG-NEXT: TEX 0 @6
834 ; EG-NEXT: TEX 0 @6
912 ; EG-NEXT: TEX 0 @6
1014 ; EG-NEXT: TEX 0 @6
[all …]
H A Dsra.ll50 ; EG-NEXT: TEX 0 @6
120 ; EG-NEXT: TEX 1 @6
208 ; EG-NEXT: TEX 0 @6
327 ; EG-NEXT: TEX 0 @6
492 ; EG-NEXT: TEX 0 @6
566 ; EG-NEXT: TEX 1 @6
662 ; EG-NEXT: TEX 3 @6
817 ; EG-NEXT: TEX 0 @6
938 ; EG-NEXT: TEX 0 @6
H A Dcttz_zero_undef.ll106 ; EG-NEXT: TEX 0 @6
183 ; EG-NEXT: TEX 0 @6
266 ; EG-NEXT: TEX 0 @6
336 ; EG-NEXT: TEX 0 @6
407 ; EG-NEXT: TEX 0 @6
610 ; EG-NEXT: TEX 0 @6
709 ; EG-NEXT: TEX 0 @6
830 ; EG-NEXT: TEX 1 @6
996 ; EG-NEXT: TEX 3 @6
1139 ; EG-NEXT: TEX 1 @6
[all …]
H A Dshl.ll48 ; EG-NEXT: TEX 0 @6
115 ; EG-NEXT: TEX 1 @6
182 ; EG-NEXT: TEX 1 @6
256 ; EG-NEXT: TEX 1 @6
331 ; EG-NEXT: TEX 0 @8
333 ; EG-NEXT: TEX 0 @10
427 ; EG-NEXT: TEX 0 @8
500 ; EG-NEXT: TEX 0 @6
589 ; EG-NEXT: TEX 0 @8
685 ; EG-NEXT: TEX 0 @6
[all …]
H A Dcttz.ll132 ; EG-NEXT: TEX 0 @6
229 ; EG-NEXT: TEX 0 @6
341 ; EG-NEXT: TEX 0 @6
452 ; EG-NEXT: TEX 0 @6
720 ; EG-NEXT: TEX 0 @6
832 ; EG-NEXT: TEX 0 @6
937 ; EG-NEXT: TEX 0 @6
1033 ; EG-NEXT: TEX 0 @6
1136 ; EG-NEXT: TEX 0 @6
1243 ; EG-NEXT: TEX 0 @6
[all …]
H A Dload-global-i16.ll61 ; EG-NEXT: TEX 0 @6
87 ; CM-NEXT: TEX 0 @6
166 ; EG-NEXT: TEX 0 @6
182 ; CM-NEXT: TEX 0 @6
258 ; EG-NEXT: TEX 2 @6
294 ; CM-NEXT: TEX 2 @6
383 ; EG-NEXT: TEX 0 @6
399 ; CM-NEXT: TEX 0 @6
468 ; EG-NEXT: TEX 0 @6
484 ; CM-NEXT: TEX 0 @6
[all …]
H A Dctlz.ll147 ; EG-NEXT: TEX 0 @6
259 ; EG-NEXT: TEX 0 @6
389 ; EG-NEXT: TEX 0 @6
526 ; EG-NEXT: TEX 0 @6
850 ; EG-NEXT: TEX 0 @6
980 ; EG-NEXT: TEX 0 @6
1103 ; EG-NEXT: TEX 0 @6
1212 ; EG-NEXT: TEX 0 @6
1328 ; EG-NEXT: TEX 0 @6
1452 ; EG-NEXT: TEX 0 @6
[all …]
H A Drv7x0_count3.ll3 ; CHECK: TEX 9 @6 ; encoding: [0x06,0x00,0x00,0x00,0x00,0x04,0x88,0x80]
H A Dload-constant-i16.ll58 ; EG-NEXT: TEX 0 @6
126 ; EG-NEXT: TEX 0 @6
195 ; EG-NEXT: TEX 2 @6
276 ; EG-NEXT: TEX 0 @6
343 ; EG-NEXT: TEX 0 @6
430 ; EG-NEXT: TEX 0 @8
580 ; EG-NEXT: TEX 0 @8
653 ; EG-NEXT: TEX 0 @6
722 ; EG-NEXT: TEX 0 @6
792 ; EG-NEXT: TEX 0 @6
[all …]
H A Dsdiv.ll155 ; EG-NEXT: TEX 0 @6
267 ; EG-NEXT: TEX 0 @6
367 ; EG-NEXT: TEX 0 @6
615 ; EG-NEXT: TEX 0 @6
764 ; EG-NEXT: TEX 0 @6
1191 ; EG-NEXT: TEX 1 @6
1415 ; EG-NEXT: TEX 0 @6
1559 ; EG-NEXT: TEX 1 @6
1734 ; EG-NEXT: TEX 3 @6
1917 ; EG-NEXT: TEX 3 @6
[all …]
H A Dudiv.ll145 ; EG-NEXT: TEX 0 @6
551 ; EG-NEXT: TEX 0 @6
981 ; EG-NEXT: TEX 1 @6
1131 ; EG-NEXT: TEX 0 @6
1223 ; EG-NEXT: TEX 0 @6
1317 ; EG-NEXT: TEX 0 @6
1444 ; EG-NEXT: TEX 1 @6
1593 ; EG-NEXT: TEX 1 @6
1782 ; EG-NEXT: TEX 3 @6
2018 ; EG-NEXT: TEX 3 @6
[all …]
H A Dfp_to_uint.ll124 ; EG-NEXT: TEX 0 @6
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600Defines.h30 TEX = (1 << 1), enumerator
H A DEvergreenInstructions.td835 "TEX $COUNT @$ADDR"> {
H A DR600Instructions.td1289 "TEX $CNT @$ADDR"> {

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