| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | Thumb2ITBlockPass.cpp | 101 for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true); in INITIALIZE_PASS() local
102 Subreg.isValid(); ++Subreg) in INITIALIZE_PASS()
103 UsesDefs.insert(*Subreg); in INITIALIZE_PASS()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCReduceCRLogicals.cpp | 411 MachineInstr *lookThroughCRCopy(unsigned Reg, unsigned &Subreg,
536 unsigned &Subreg, in lookThroughCRCopy() argument
538 Subreg = -1; in lookThroughCRCopy()
546 Subreg = Copy->getOperand(1).getSubReg(); in lookThroughCRCopy()
551 Subreg = PPC::sub_eq; in lookThroughCRCopy()
553 Subreg = PPC::sub_lt; in lookThroughCRCopy()
555 Subreg = PPC::sub_gt; in lookThroughCRCopy()
557 Subreg = PPC::sub_un; in lookThroughCRCopy()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86FixupBWInsts.cpp | 311 unsigned Subreg = TRI->getSubRegIndex(MIB->getOperand(0).getReg(), in tryReplaceLoad() local
314 MF->makeDebugValueSubstitution({OldInstrNum, 0}, {NewInstrNum, 0}, Subreg); in tryReplaceLoad()
381 unsigned Subreg = TRI->getSubRegIndex(MIB->getOperand(0).getReg(), in tryReplaceExtend() local
384 MF->makeDebugValueSubstitution({OldInstrNum, 0}, {NewInstrNum, 0}, Subreg); in tryReplaceExtend()
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| H A D | X86InstrAVX512.td | 1359 RegisterClass SrcRC, SubRegIndex Subreg> {
1370 (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SrcRC:$src, Subreg)))>;
1375 (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SrcRC:$src, Subreg)))>;
1379 (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SrcRC:$src, Subreg)))>;
1384 RegisterClass SrcRC, SubRegIndex Subreg, Predicate prd> {
1387 OpNode, SrcRC, Subreg>, EVEX_V512;
1390 _.info256, OpNode, SrcRC, Subreg>, EVEX_V256;
1392 _.info128, OpNode, SrcRC, Subreg>, EVEX_V128;
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| /llvm-project-15.0.7/llvm/test/DebugInfo/MIR/InstrRef/ |
| H A D | x86-fixup-bw-inst-subreb.mir | 23 ## Subreg 4 -> sub_16bit
43 ## Subreg 4 -> sub_16bit
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | MachineFunction.h | 488 unsigned Subreg; ///< Qualifier for which part of Dest is read.
491 const DebugInstrOperandPair &Dest, unsigned Subreg)
492 : Src(Src), Dest(Dest), Subreg(Subreg) {}
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| H A D | MIRYamlMapping.h | 495 unsigned Subreg;
509 YamlIO.mapRequired("subreg", Sub.Subreg);
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| H A D | SelectionDAG.h | 1644 SDValue Operand, SDValue Subreg);
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| /llvm-project-15.0.7/llvm/lib/CodeGen/LiveDebugValues/ |
| H A D | InstrRefBasedImpl.cpp | 1139 if (unsigned Subreg = LowerBoundIt->Subreg) in transferDebugInstrRef() local
1140 SeenSubregs.push_back(Subreg); in transferDebugInstrRef()
1210 for (unsigned Subreg : reverse(SeenSubregs)) { in transferDebugInstrRef() local
1211 unsigned ThisSize = TRI->getSubRegIdxSize(Subreg); in transferDebugInstrRef()
1212 unsigned ThisOffset = TRI->getSubRegIdxOffset(Subreg); in transferDebugInstrRef()
1239 unsigned Subreg = TRI->getSubRegIndex(Reg, *SRI); in transferDebugInstrRef() local
1240 unsigned SubregSize = TRI->getSubRegIdxSize(Subreg); in transferDebugInstrRef()
1241 unsigned SubregOffset = TRI->getSubRegIdxOffset(Subreg); in transferDebugInstrRef()
1693 unsigned Subreg = TRI->getSubRegIndex(Reg, *SRI); in transferSpillOrRestoreInst() local
1694 unsigned SpillID = MTracker->getLocID(*Loc, Subreg); in transferSpillOrRestoreInst()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | MachineFunction.cpp | 977 unsigned Subreg) { in makeDebugValueSubstitution() argument
983 DebugValueSubstitutions.push_back({A, B, Subreg}); in makeDebugValueSubstitution()
1118 for (unsigned Subreg : reverse(SubregsSeen)) { in salvageCopySSAImpl() local
1123 makeDebugValueSubstitution({NewInstrNumber, 0}, P, Subreg); in salvageCopySSAImpl()
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| H A D | MIRPrinter.cpp | 229 Sub.Subreg}); in print()
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| /llvm-project-15.0.7/llvm/test/CodeGen/ARM/ |
| H A D | regcoal-invalid-subrange-update.mir | 39 # 3. Subreg liveness enabled.
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIRParser.cpp | 442 {Sub.DstInst, Sub.DstOp}, Sub.Subreg); in setupDebugValueTracking()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 9773 SDNode *Subreg = getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, in getTargetExtractSubreg() local
9775 return SDValue(Subreg, 0); in getTargetExtractSubreg()
9781 SDValue Operand, SDValue Subreg) { in getTargetInsertSubreg() argument
9784 VT, Operand, Subreg, SRIdxVal); in getTargetInsertSubreg()
|