| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InterleavedAccess.cpp | 168 Instruction *VecInst, unsigned NumSubVectors, FixedVectorType *SubVecTy, in decompose() argument
177 DL.getTypeSizeInBits(SubVecTy) * NumSubVectors && in decompose()
189 createSequentialMask(Indices[i], SubVecTy->getNumElements(), in decompose()
209 VecBaseTy = SubVecTy; in decompose()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 1528 auto *SubVecTy = in getInterleavedMemoryOpCost() local
1537 TLI->isLegalInterleavedAccessType(Factor, SubVecTy, Alignment, DL)) in getInterleavedMemoryOpCost()
1538 return Factor * BaseCost * TLI->getNumInterleavedAccesses(SubVecTy, DL); in getInterleavedMemoryOpCost()
1547 DL.getTypeSizeInBits(SubVecTy).getFixedSize() <= 64) in getInterleavedMemoryOpCost()
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| H A D | ARMISelLowering.cpp | 21495 auto *SubVecTy = FixedVectorType::get(EltTy, LaneLen); in lowerInterleavedStore() local
21503 if (!isLegalInterleavedAccessType(Factor, SubVecTy, Alignment, DL)) in lowerInterleavedStore()
21506 unsigned NumStores = getNumInterleavedAccesses(SubVecTy, DL); in lowerInterleavedStore()
21523 SubVecTy = FixedVectorType::get(IntTy, LaneLen); in lowerInterleavedStore()
21533 SubVecTy = FixedVectorType::get(SubVecTy->getElementType(), LaneLen); in lowerInterleavedStore()
21540 SubVecTy->getElementType()->getPointerTo(SI->getPointerAddressSpace())); in lowerInterleavedStore()
21543 assert(isTypeLegal(EVT::getEVT(SubVecTy)) && "Illegal vstN vector type!"); in lowerInterleavedStore()
21554 Type *Tys[] = {Int8Ptr, SubVecTy}; in lowerInterleavedStore()
21569 Type *EltPtrTy = SubVecTy->getElementType()->getPointerTo( in lowerInterleavedStore()
21571 Type *Tys[] = {EltPtrTy, SubVecTy}; in lowerInterleavedStore()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 2326 auto *SubVecTy = in getInterleavedMemoryOpCost() local
2334 TLI->isLegalInterleavedAccessType(SubVecTy, DL, UseScalable)) in getInterleavedMemoryOpCost()
2335 return Factor * TLI->getNumInterleavedAccesses(SubVecTy, DL, UseScalable); in getInterleavedMemoryOpCost()
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| H A D | AArch64ISelLowering.cpp | 13214 auto *SubVecTy = FixedVectorType::get(EltTy, LaneLen); in lowerInterleavedStore() local
13223 !isLegalInterleavedAccessType(SubVecTy, DL, UseScalable)) in lowerInterleavedStore()
13226 unsigned NumStores = getNumInterleavedAccesses(SubVecTy, DL, UseScalable); in lowerInterleavedStore()
13244 SubVecTy = FixedVectorType::get(IntTy, LaneLen); in lowerInterleavedStore()
13250 SubVecTy = FixedVectorType::get(SubVecTy->getElementType(), LaneLen); in lowerInterleavedStore()
13252 auto *STVTy = UseScalable ? cast<VectorType>(getSVEContainerIRType(SubVecTy)) in lowerInterleavedStore()
13253 : SubVecTy; in lowerInterleavedStore()
13264 SubVecTy->getElementType()->getPointerTo(SI->getPointerAddressSpace())); in lowerInterleavedStore()
13293 getSVEPredPatternFromNumElements(SubVecTy->getNumElements()); in lowerInterleavedStore()
13297 DL.getTypeSizeInBits(SubVecTy)) in lowerInterleavedStore()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCalls.cpp | 2368 auto *SubVecTy = dyn_cast<FixedVectorType>(SubVec->getType()); in visitCallInst() local
2372 if (DstTy && VecTy && SubVecTy) { in visitCallInst()
2375 unsigned SubVecNumElts = SubVecTy->getNumElements(); in visitCallInst()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 1065 MVT SubVecTy = tyVector(ty(Ext), ElemTy); in insertHvxElementReg() local
1066 SDValue Ins = insertVector(DAG.getBitcast(SubVecTy, Ext), in insertHvxElementReg()
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| /llvm-project-15.0.7/llvm/lib/IR/ |
| H A D | Verifier.cpp | 5580 VectorType *SubVecTy = cast<VectorType>(SubVec->getType()); in visitIntrinsicCall() local
5583 ElementCount SubVecEC = SubVecTy->getElementCount(); in visitIntrinsicCall()
5584 Check(VecTy->getElementType() == SubVecTy->getElementType(), in visitIntrinsicCall()
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| /llvm-project-15.0.7/clang/include/clang/Basic/ |
| H A D | riscv_vector.td | 2175 // C/C++ Operand: SubVecTy, IR Operand: VecTy, SubVecTy, Index
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