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Searched refs:SubRegIndices (Results 1 – 25 of 32) sorted by relevance

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/llvm-project-15.0.7/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp171 if (!SubRegIndices.empty()) { in runEnums()
178 for (const auto &Idx : SubRegIndices) in runEnums()
715 std::distance(SubRegIndices.begin(), SubRegIndices.end()); in emitComposeSubRegIndices()
716 for (const auto &Idx : SubRegIndices) { in emitComposeSubRegIndices()
775 for (const auto &Idx : SubRegIndices) { in emitComposeSubRegIndexLaneMask()
1131 << (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n" in runMCDesc()
1350 for (auto &Idx : SubRegIndices) { in runTargetDesc()
1506 std::distance(SubRegIndices.begin(), SubRegIndices.end()); in runTargetDesc()
1508 if (!SubRegIndices.empty()) { in runTargetDesc()
1514 if (!SubRegIndices.empty()) { in runTargetDesc()
[all …]
H A DCodeGenRegisters.cpp1162 for (auto &Idx : SubRegIndices) in CodeGenRegBank()
1271 SubRegIndices.emplace_back(Name, Namespace, SubRegIndices.size() + 1); in createSubRegIndex()
1272 return &SubRegIndices.back(); in createSubRegIndex()
1279 SubRegIndices.emplace_back(Def, SubRegIndices.size() + 1); in getSubRegIdx()
1280 Idx = &SubRegIndices.back(); in getSubRegIdx()
1490 for (auto &Idx : SubRegIndices) { in computeSubRegLaneMasks()
1511 for (const auto &Idx : SubRegIndices) { in computeSubRegLaneMasks()
1530 for (auto &Idx2 : SubRegIndices) { in computeSubRegLaneMasks()
1586 for (const auto &Idx : SubRegIndices) { in computeSubRegLaneMasks()
2255 for (const auto &SubIdx : SubRegIndices) { in inferSubClassWithSubReg()
[all …]
H A DCodeGenRegisters.h552 std::deque<CodeGenSubRegIndex> SubRegIndices; variable
656 return SubRegIndices; in getSubRegIndices()
/llvm-project-15.0.7/llvm/test/TableGen/
H A Dambiguous-composition.td47 let SubRegIndices = [subreg_h32];
51 let SubRegIndices = [subreg_h64, subreg_h32];
55 let SubRegIndices = [subreg_h64];
79 let SubRegIndices = [subreg_l32];
83 let SubRegIndices = [subreg_l64];
H A DGlobalISelEmitter-nested-subregs.td20 let SubRegIndices = [hi8, lo8];
25 let SubRegIndices = [hi16, lo16];
H A DGlobalISelEmitterRegSequence.td23 let SubRegIndices = [sub0, sub1] in {
/llvm-project-15.0.7/llvm/lib/MC/
H A DMCRegisterInfo.cpp37 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubReg()
49 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubRegIndex()
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCRegisterInfo.h112 uint32_t SubRegIndices; member
169 const uint16_t *SubRegIndices; // Pointer to the subreg lookup variable
378 SubRegIndices = SubIndices; in InitMCRegisterInfo()
619 SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices; in MCSubRegIndexIterator()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVERegisterInfo.td115 let SubRegIndices = [sub_i32, sub_f32], CoveredBySubRegs = 1 in {
136 let SubRegIndices = [sub_even, sub_odd], CoveredBySubRegs = 1 in
157 let SubRegIndices = [sub_vm_even, sub_vm_odd], CoveredBySubRegs = 1 in
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td46 let SubRegIndices = [sub_32];
55 let SubRegIndices = [sub_lo, sub_hi];
61 let SubRegIndices = [sub_lo, sub_hi];
68 let SubRegIndices = [sub_64];
74 let SubRegIndices = [sub_lo, sub_hi];
190 let SubRegIndices = [sub_32] in {
246 let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22,
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td70 let SubRegIndices = [subreg_l32, subreg_h32];
78 let SubRegIndices = [subreg_l64, subreg_h64];
213 let SubRegIndices = [subreg_h32];
220 let SubRegIndices = [subreg_l64, subreg_h64];
256 let SubRegIndices = [subreg_h64];
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td28 let SubRegIndices = [sub_16];
40 let SubRegIndices = [sub_32];
433 let SubRegIndices = [sub_vrm1_0, sub_vrm1_1];
443 let SubRegIndices = [sub_vrm2_0, sub_vrm2_1];
453 let SubRegIndices = [sub_vrm4_0, sub_vrm4_1];
558 let SubRegIndices = [sub_32, sub_32_hi];
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfoMMA.td38 let SubRegIndices = [sub_pair0, sub_pair1] in {
60 let SubRegIndices = [sub_pair0, sub_pair1] in {
H A DPPCRegisterInfo.td41 let SubRegIndices = [sub_32];
48 let SubRegIndices = [sub_32];
73 let SubRegIndices = [sub_64];
81 let SubRegIndices = [sub_64];
113 let SubRegIndices = [sub_gp8_x0, sub_gp8_x1];
165 let SubRegIndices = [sub_vsx0, sub_vsx1] in {
234 let SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in {
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.td28 let SubRegIndices = [sub_32];
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86RegisterInfo.td114 let SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in {
120 let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in {
129 let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CostPerUse = [1],
142 let SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in {
155 let SubRegIndices = [sub_16bit, sub_16bit_hi], CostPerUse = [1],
168 let SubRegIndices = [sub_32bit] in {
253 let SubRegIndices = [sub_xmm] in {
261 let SubRegIndices = [sub_ymm] in {
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td136 let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in {
168 let SubRegIndices = [subreg_overflow];
205 let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in {
231 let SubRegIndices = [vsub_lo, vsub_hi, vsub_fake], CoveredBySubRegs = 1 in {
251 let SubRegIndices = [vsub_lo, vsub_hi, vsub_fake], CoveredBySubRegs = 1 in {
271 let SubRegIndices = [wsub_lo, wsub_hi], CoveredBySubRegs = 1 in {
372 let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in {
451 let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in {
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td163 let SubRegIndices = [lo16, hi16];
191 let SubRegIndices = [sub0, sub1];
200 let SubRegIndices = [sub0, sub1];
228 let SubRegIndices = [sub0, sub1];
254 let SubRegIndices = [sub0, sub1];
264 let SubRegIndices = [sub0, sub1];
273 let SubRegIndices = [sub0, sub1];
292 let SubRegIndices = [sub0, sub1];
449 let SubRegIndices = indices;
H A DR600RegisterInfo.td23 let SubRegIndices = [sub0, sub1, sub2, sub3];
32 let SubRegIndices = [sub0, sub1];
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td30 let SubRegIndices = [sub_32] in {
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td102 let SubRegIndices = [sub_32] in {
293 let SubRegIndices = [bsub] in {
328 let SubRegIndices = [hsub] in {
363 let SubRegIndices = [ssub], RegAltNameIndices = [vreg, vlist1] in {
398 let SubRegIndices = [dsub], RegAltNameIndices = [vreg, vlist1] in {
804 let SubRegIndices = [zsub,zsub_hi] in {
1182 let SubRegIndices = [zasubq0, zasubq1] in {
1193 let SubRegIndices = [zasubd0, zasubd1] in {
1200 let SubRegIndices = [zasubs0, zasubs1] in {
1205 let SubRegIndices = [zasubh0, zasubh1] in {
[all …]
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td35 let SubRegIndices = [sub32_0];
43 let SubRegIndices = [sub64_0];
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.td54 let SubRegIndices = [subreg_8bit] in {
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td37 let SubRegIndices = [sub_even, sub_odd];
46 let SubRegIndices = [sub_even, sub_odd];
53 let SubRegIndices = [sub_even64, sub_odd64];
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kRegisterInfo.td23 let SubRegIndices = SUBIDX;

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