| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 207 unsigned SubReg1; in isProfitableToTransform() local
225 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1); in isProfitableToTransform()
299 unsigned Src1 = 0, SubReg1; in transformInstruction() local
324 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1); in transformInstruction()
348 SubReg1 = 0; in transformInstruction()
364 .addReg(Src1, getKillRegState(KillSrc1), SubReg1); in transformInstruction()
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| H A D | AArch64ISelLowering.cpp | 20144 SDValue SubReg1 = DAG.getTargetConstant(AArch64::subo64, dl, MVT::i32); in createGPRPairNode() local
20145 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 }; in createGPRPairNode()
20191 unsigned SubReg1 = AArch64::sube64, SubReg2 = AArch64::subo64; in ReplaceCMP_SWAP_128Results() local
20193 std::swap(SubReg1, SubReg2); in ReplaceCMP_SWAP_128Results()
20194 SDValue Lo = DAG.getTargetExtractSubreg(SubReg1, SDLoc(N), MVT::i64, in ReplaceCMP_SWAP_128Results()
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| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelDAGToDAG.cpp | 377 SDValue SubReg1 = CurDAG->getTargetConstant(CSKY::sub32_32, dl, MVT::i32); in createGPRPairNode() local
378 const SDValue Ops[] = {RegClass, V0, SubReg0, V1, SubReg1}; in createGPRPairNode()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 186 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg(); in commuteInstructionImpl() local
213 SubReg0 = SubReg1; in commuteInstructionImpl()
231 CommutedMI->getOperand(Idx2).setSubReg(SubReg1); in commuteInstructionImpl()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1845 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32); in createGPRPairNode() local
1846 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode()
1856 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createSRegPairNode() local
1857 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createSRegPairNode()
1867 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); in createDRegPairNode() local
1868 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createDRegPairNode()
1878 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); in createQRegPairNode() local
1879 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createQRegPairNode()
1893 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadSRegsNode()
1908 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadDRegsNode()
[all …]
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| H A D | ARMISelLowering.cpp | 10249 SDValue SubReg1 = DAG.getTargetConstant(ARM::gsub_1, dl, MVT::i32); in createGPRPairNode() local
10250 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 }; in createGPRPairNode()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 586 SDValue RC, SubReg0, SubReg1; in Select() local
591 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32); in Select()
595 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in Select()
600 N->getOperand(1), SubReg1 }; in Select()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1174 unsigned SubReg1 = MI.getOperand(1).getSubReg(); in commuteInstructionImpl() local
1185 assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch"); in commuteInstructionImpl()
1217 MI.getOperand(2).setSubReg(SubReg1); in commuteInstructionImpl()
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