| /llvm-project-15.0.7/clang/test/CodeGenObjC/ |
| H A D | category-super-class-meth.m | 15 @interface Sub2 : NSObject @end interface
17 @interface Sub2 (Category) @end interface in Category
19 @implementation Sub2 (Category) implementation in Category
24 // CHECK: define internal i8* @"\01+[Sub2(Category) copy]
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| /llvm-project-15.0.7/clang/test/Modules/Inputs/odr_hash-Unresolved/ |
| H A D | module.modulemap | 7 module Sub2 {
8 umbrella "Sub2"
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| /llvm-project-15.0.7/clang/test/Index/ |
| H A D | annotate-module.m | 32 …] inclusion directive=[[INC_DIR:Module[/\\]Sub2\.h \(.*/Modules/Inputs/Module\.framework[/\\]Heade…
37 // CHECK-MOD-NEXT: Identifier: "Sub2" [1:18 - 1:22] inclusion directive=[[INC_DIR]]
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| H A D | index-module.m | 49 // CHECK-TMOD-NEXT: [ppIncludedFile]: [[TMODHDR]]Sub2.h | name: "Module/Sub2.h" | hash loc: [[TMODH…
63 …on]: kind: variable | name: Module_Sub2 | USR: c:@Module_Sub2 | {{.*}} | loc: [[TMODHDR]]Sub2.h:1:6
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| /llvm-project-15.0.7/clang/test/Modules/Inputs/ |
| H A D | MethodPoolASub2.h | 1 @interface A (Sub2)
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| H A D | module.map | 139 explicit module Sub2 {
150 explicit module Sub2 {
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| /llvm-project-15.0.7/clang/test/Modules/ |
| H A D | submodules.m | 6 // Note: transitively imports Module.Sub2.
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| H A D | dependency-dump-dependent-module.m | 14 // VFS: 'name': "Sub2.h"
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| H A D | dependency-dump.m | 13 // VFS: 'name': "Sub2.h"
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| /llvm-project-15.0.7/llvm/test/TableGen/ |
| H A D | SuperSubclassSameName.td | 21 class Sub2<int F> : Super2<F>;
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| /llvm-project-15.0.7/clang/test/FixIt/ |
| H A D | typo.m | 116 @interface Sub2 : Super interface
120 @implementation Sub2 implementation
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| /llvm-project-15.0.7/clang/test/ARCMT/Inputs/ |
| H A D | module.map | 134 explicit module Sub2 {
145 explicit module Sub2 {
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| /llvm-project-15.0.7/clang/test/CodeGenObjCXX/ |
| H A D | encode.mm | 146 struct Sub2 : public Sub_with_virt, public Base1, virtual DBase { struct
159 // CHECK: @g4 ={{.*}} constant [19 x i8] c"{Sub2=^^?qcf^^?cd}\00"
160 extern const char g4[] = @encode(Sub2);
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 1541 unsigned Sub2 = DI->getOperand(2).getImm(); in checkForImmediate() local
1543 if (Sub2 == Hexagon::isub_lo && Sub4 == Hexagon::isub_hi) in checkForImmediate()
1545 else if (Sub2 == Hexagon::isub_hi && Sub4 == Hexagon::isub_lo) in checkForImmediate()
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| H A D | HexagonBitSimplify.cpp | 466 unsigned Sub1 = I.getOperand(2).getImm(), Sub2 = I.getOperand(4).getImm(); in parseRegSequence() local
472 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence()
473 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence()
478 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence()
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| H A D | HexagonConstPropagation.cpp | 1952 unsigned Sub2 = MI.getOperand(4).getImm(); in evaluate() local
1958 if (Sub2 != SubLo && Sub2 != SubHi) in evaluate()
1960 assert(Sub1 != Sub2); in evaluate()
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| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 1400 const CodeGenSubRegIndex *Sub2) { in computeComposites() argument
1403 const RegMap &Img2 = SubRegAction.at(Sub2); in computeComposites()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1818 SDValue Sub2 = DAG.getBitcast(VT, in LowerUDIVREM64() local
1847 SDValue Sel2 = DAG.getSelectCC(DL, C6, Zero, Sub3, Sub2, ISD::SETNE); in LowerUDIVREM64()
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| H A D | AMDGPULegalizerInfo.cpp | 3602 auto Sub2 = B.buildMerge(S64, {Sub2_Lo, Sub2_Hi}); in legalizeUnsignedDIV_REM64Impl() local
3634 S64, B.buildICmp(CmpInst::ICMP_NE, S1, C6, Zero32), Sub3, Sub2); in legalizeUnsignedDIV_REM64Impl()
|