Home
last modified time | relevance | path

Searched refs:Stage (Results 1 – 25 of 45) sorted by relevance

12

/llvm-project-15.0.7/llvm/include/llvm/MCA/Stages/
H A DStage.h27 class Stage {
28 Stage *NextInSequence;
31 Stage(const Stage &Other) = delete;
32 Stage &operator=(const Stage &Other) = delete;
38 Stage() : NextInSequence(nullptr) {} in Stage() function
39 virtual ~Stage();
60 void setNextInSequence(Stage *NextStage) { in setNextInSequence()
H A DInstructionTables.h28 class InstructionTables final : public Stage {
H A DEntryStage.h26 class EntryStage final : public Stage {
H A DRetireStage.h28 class RetireStage final : public Stage {
H A DDispatchStage.h49 class DispatchStage final : public Stage {
H A DMicroOpQueueStage.h26 class MicroOpQueueStage : public Stage {
/llvm-project-15.0.7/llvm/lib/MCA/
H A DInstruction.cpp154 Stage = IS_INVALID; in reset()
164 assert(Stage == IS_INVALID); in dispatch()
165 Stage = IS_DISPATCHED; in dispatch()
174 assert(Stage == IS_READY); in execute()
175 Stage = IS_EXECUTING; in execute()
185 Stage = IS_EXECUTED; in execute()
189 assert(Stage == IS_READY && "Invalid internal state!"); in forceExecuted()
191 Stage = IS_EXECUTED; in forceExecuted()
204 Stage = IS_READY; in updatePending()
221 Stage = IS_PENDING; in updateDispatched()
[all …]
H A DPipeline.cpp32 return any_of(Stages, [](const std::unique_ptr<Stage> &S) { in hasWorkToProcess()
56 const std::unique_ptr<Stage> &S = *I; in runCycle()
67 Stage &FirstStage = *Stages[0]; in runCycle()
77 for (const std::unique_ptr<Stage> &S : Stages) { in runCycle()
86 void Pipeline::appendStage(std::unique_ptr<Stage> S) { in appendStage()
89 Stage *Last = Stages.back().get(); in appendStage()
H A DCMakeLists.txt23 Stages/Stage.cpp
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/pipeliner/
H A Dswp-phi-start.mir6 # CHECK-NOT: Stage-3
8 # CHECK: intregs = S2_addasl_rrri %{{[0-9]+}}, %{{[0-9]+}}, 1, post-instr-symbol <mcsymbol Stage…
9 # CHECK: intregs = L2_loadruh_io %{{[0-9]+}}, -4, post-instr-symbol <mcsymbol Stage-3_Cycle-0> :…
11 # CHECK: intregs = nsw A2_addi %{{[0-9]+}}, -1, post-instr-symbol <mcsymbol Stage-0_Cycle-0>
13 # CHECK-NOT: Stage-0
138 %1:intregs = PHI %7, %bb.2, %5, %bb.3, post-instr-symbol <mcsymbol Stage-3_Cycle-0>
139 %2:intregs = PHI %10, %bb.2, %4, %bb.3, post-instr-symbol <mcsymbol Stage-0_Cycle-0>
140 %3:intregs = PHI %6, %bb.2, %2, %bb.3, post-instr-symbol <mcsymbol Stage-0_Cycle-0>
141 %11:intregs = S2_addasl_rrri %7, %3, 1, post-instr-symbol <mcsymbol Stage-0_Cycle-0>
142 …%12:intregs = L2_loadruh_io %11, -4, post-instr-symbol <mcsymbol Stage-3_Cycle-0> :: (load (s16) f…
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DModuloSchedule.h93 DenseMap<MachineInstr *, int> Stage; variable
109 DenseMap<MachineInstr *, int> Stage) in ModuloSchedule() argument
111 Stage(std::move(Stage)) { in ModuloSchedule()
113 for (auto &KV : this->Stage) in ModuloSchedule()
135 auto I = Stage.find(MI); in getStage()
136 return I == Stage.end() ? -1 : I->second; in getStage()
147 assert(Stage.count(MI) == 0); in setStage()
148 Stage[MI] = MIStage; in setStage()
341 MachineBasicBlock *SourceBB, unsigned Stage);
/llvm-project-15.0.7/llvm/lib/MCA/Stages/
H A DStage.cpp21 Stage::~Stage() = default;
23 void Stage::addListener(HWEventListener *Listener) { in addListener()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DGCNSchedStrategy.h90 inline GCNSchedStageID &operator++(GCNSchedStageID &Stage, int) {
91 assert(Stage != GCNSchedStageID::PreRARematerialize);
92 Stage = static_cast<GCNSchedStageID>(static_cast<unsigned>(Stage) + 1);
93 return Stage;
96 inline GCNSchedStageID nextStage(const GCNSchedStageID Stage) { in nextStage() argument
97 return static_cast<GCNSchedStageID>(static_cast<unsigned>(Stage) + 1); in nextStage()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRegAllocGreedy.h69 LiveRangeStage Stage = RS_New; member
85 LiveRangeStage getStage(Register Reg) const { return Info[Reg].Stage; } in getStage()
91 void setStage(Register Reg, LiveRangeStage Stage) { in setStage() argument
93 Info[Reg].Stage = Stage; in setStage()
96 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage() argument
97 setStage(VirtReg.reg(), Stage); in setStage()
135 if (Info[Reg].Stage == RS_New) in setStage()
136 Info[Reg].Stage = NewStage; in setStage()
H A DModuloSchedule.cpp1596 int Stage = getStage(MI); in filterInstructions() local
1597 if (Stage == -1 || Stage >= MinStage) in filterInstructions()
1629 if (getStage(&MI) != Stage) { in moveStageBetweenBlocks()
1644 if (getStage(&MI) != Stage) in moveStageBetweenBlocks()
1658 if (getStage(Def) == Stage) { in moveStageBetweenBlocks()
1775 unsigned Stage = Schedule.getNumStages() - 1 + I - J; in peelPrologAndEpilogs() local
1779 LS[Stage] = true; in peelPrologAndEpilogs()
1908 int Stage = getStage(MI); in rewriteUsesOf() local
1910 LiveStages[MI->getParent()].test(Stage)) in rewriteUsesOf()
2160 DenseMap<MachineInstr *, int> Cycle, Stage; in runOnLoop() local
[all …]
H A DRegAllocGreedy.cpp267 Info[Old].Stage = RS_Assign; in LRE_DidCloneVirtReg()
287 auto Stage = ExtraInfo->getOrInitStage(Reg); in enqueue() local
288 if (Stage == RS_New) { in enqueue()
289 Stage = RS_Assign; in enqueue()
290 ExtraInfo->setStage(Reg, Stage); in enqueue()
292 if (Stage == RS_Split) { in enqueue()
296 } else if (Stage == RS_Memory) { in enqueue()
2253 if (Stage != RS_Split) in selectOrSplitImpl()
2273 if (Stage < RS_Split) { in selectOrSplitImpl()
2280 if (Stage < RS_Spill) { in selectOrSplitImpl()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/MCA/
H A DInstruction.h612 enum InstrStage Stage; variable
648 : InstructionBase(D, Opcode), Stage(IS_INVALID), in Instruction()
684 bool isInvalid() const { return Stage == IS_INVALID; } in isInvalid()
685 bool isDispatched() const { return Stage == IS_DISPATCHED; } in isDispatched()
686 bool isPending() const { return Stage == IS_PENDING; } in isPending()
687 bool isReady() const { return Stage == IS_READY; } in isReady()
688 bool isExecuting() const { return Stage == IS_EXECUTING; } in isExecuting()
689 bool isExecuted() const { return Stage == IS_EXECUTED; } in isExecuted()
690 bool isRetired() const { return Stage == IS_RETIRED; } in isRetired()
699 Stage = IS_RETIRED; in retire()
H A DPipeline.h62 SmallVector<std::unique_ptr<Stage>, 8> Stages;
73 void appendStage(std::unique_ptr<Stage> S);
/llvm-project-15.0.7/llvm/utils/docker/nvidia-cuda/
H A DDockerfile8 # Stage 1. Check out LLVM source code and run the build.
28 # Stage 2. Produce a minimal release image with build results.
/llvm-project-15.0.7/llvm/utils/docker/example/
H A DDockerfile11 # Stage 1. Check out LLVM source code and run the build.
30 # Stage 2. Produce a minimal release image with build results.
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A D2013-04-16-AAPCS-C5-vs-VFP.ll1 ;Check 5.5 Parameter Passing --> Stage C --> C.5 statement, when NSAA is not
14 ;please, read 5.5 Parameter Passing, Stage C, stages C.2.cp, C.4 and C.5
/llvm-project-15.0.7/llvm/test/Linker/
H A Ddebug-info-bad-enum.ll26 !3 = !DICompositeType(tag: DW_TAG_enumeration_type, name: "Stage", file: !1, line: 3, baseType: !4,…
44 !8 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "Stage", file: !3, line: 3, size: 64, …
/llvm-project-15.0.7/llvm/utils/docker/debian10/
H A DDockerfile8 # Stage 1. Check out LLVM source code and run the build.
39 # Stage 2. Produce a minimal release image with build results.
/llvm-project-15.0.7/llvm/docs/Proposals/
H A DVectorPredication.rst73 lower to VP SDNodes (from Stage 2).
76 - InstCombine/InstSimplify expect predication in regular Instructions (Stage (3)
/llvm-project-15.0.7/llvm/utils/gn/secondary/llvm/lib/MCA/
H A DBUILD.gn31 "Stages/Stage.cpp",

12