Searched refs:SrcReg0 (Results 1 – 5 of 5) sorted by relevance
395 Register SrcReg0 = FinalCopy0->getOperand(1).getReg(); in TEST_F() local397 KnownBits Res0 = Info.getKnownBits(SrcReg0); in TEST_F()440 Register SrcReg0 = FinalCopy0->getOperand(1).getReg(); in TEST_F() local442 KnownBits Res0 = Info.getKnownBits(SrcReg0); in TEST_F()1291 Register SrcReg0 = FinalCopy0->getOperand(1).getReg(); in TEST_F() local1293 KnownBits Res0 = Info.getKnownBits(SrcReg0); in TEST_F()1357 Register SrcReg0 = FinalCopy0->getOperand(1).getReg(); in TEST_F() local1359 KnownBits Res0 = Info.getKnownBits(SrcReg0); in TEST_F()1390 Register SrcReg0 = FinalCopy0->getOperand(1).getReg(); in TEST_F() local1392 KnownBits Res0 = Info.getKnownBits(SrcReg0); in TEST_F()[all …]
404 Register SrcReg0 = FinalCopy0->getOperand(1).getReg(); in TEST_F() local406 KnownBits Res0 = Info.getKnownBits(SrcReg0); in TEST_F()448 Register SrcReg0 = FinalCopy0->getOperand(1).getReg(); in TEST_F() local450 KnownBits Res0 = Info.getKnownBits(SrcReg0); in TEST_F()1424 Register SrcReg0 = FinalCopy0->getOperand(1).getReg(); in TEST_F() local1433 KnownBits Res0 = Info.getKnownBits(SrcReg0); in TEST_F()1494 Register SrcReg0 = FinalCopy0->getOperand(1).getReg(); in TEST_F() local1496 KnownBits Res0 = Info.getKnownBits(SrcReg0); in TEST_F()1528 Register SrcReg0 = FinalCopy0->getOperand(1).getReg(); in TEST_F() local1530 KnownBits Res0 = Info.getKnownBits(SrcReg0); in TEST_F()[all …]
433 Register SrcReg0 = MI.getOperand(1).getReg(); in optimizeVectElement() local454 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()466 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
3766 Register SrcReg0 = SrcReg; in storeRegPairToStackSlot() local3769 SrcReg0 = TRI.getSubReg(SrcReg, SubIdx0); in storeRegPairToStackSlot()3775 .addReg(SrcReg0, getKillRegState(IsKill), SubIdx0) in storeRegPairToStackSlot()5466 Register SrcReg0 = MUL->getOperand(1).getReg(); in genFusedMultiply() local5484 if (Register::isVirtualRegister(SrcReg0)) in genFusedMultiply()5485 MRI.constrainRegClass(SrcReg0, RC); in genFusedMultiply()5494 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()5656 Register SrcReg0 = MUL->getOperand(1).getReg(); in genMaddR() local5663 if (Register::isVirtualRegister(SrcReg0)) in genMaddR()5664 MRI.constrainRegClass(SrcReg0, RC); in genMaddR()[all …]
1319 Register SrcReg0 = I.getOperand(1).getReg(); in selectMergeValues() local1322 const LLT SrcTy = MRI.getType(SrcReg0); in selectMergeValues()