Lines Matching refs:SrcReg0
3766 Register SrcReg0 = SrcReg; in storeRegPairToStackSlot() local
3769 SrcReg0 = TRI.getSubReg(SrcReg, SubIdx0); in storeRegPairToStackSlot()
3775 .addReg(SrcReg0, getKillRegState(IsKill), SubIdx0) in storeRegPairToStackSlot()
5466 Register SrcReg0 = MUL->getOperand(1).getReg(); in genFusedMultiply() local
5484 if (Register::isVirtualRegister(SrcReg0)) in genFusedMultiply()
5485 MRI.constrainRegClass(SrcReg0, RC); in genFusedMultiply()
5494 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
5500 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
5506 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
5656 Register SrcReg0 = MUL->getOperand(1).getReg(); in genMaddR() local
5663 if (Register::isVirtualRegister(SrcReg0)) in genMaddR()
5664 MRI.constrainRegClass(SrcReg0, RC); in genMaddR()
5672 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genMaddR()