Searched refs:SrcOp2 (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | AsmMatcherEmitter.cpp | 1836 unsigned SrcOp2 = 0; in buildAliasResultOperands() local
1847 SrcOp2 = findAsmOperandNamed(Name, Insert.first->second); in buildAliasResultOperands()
1852 Insert.first->second = SrcOp2; in buildAliasResultOperands()
1856 SrcOp2 = (SrcOp2 == (unsigned)-1) ? SrcOp1 : SrcOp2; in buildAliasResultOperands()
1868 SrcOp2 = findAsmOperand(Name, SubIdx); in buildAliasResultOperands()
1870 ResOperand::getTiedOp((unsigned)-1, SrcOp1, SrcOp2)); in buildAliasResultOperands()
1872 ResOperands.push_back(ResOperand::getTiedOp(TiedOp, SrcOp1, SrcOp2)); in buildAliasResultOperands()
2166 uint8_t SrcOp2 = in emitConvertFuncs() local
2171 utostr(SrcOp1) + '_' + utostr(SrcOp2); in emitConvertFuncs()
2176 ConversionRow.push_back(SrcOp2); in emitConvertFuncs()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86MCInstLower.cpp | 1851 const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx); in getShuffleComment() local
1857 SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem"; in getShuffleComment()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 21567 auto SrcOp2 = Op.getOperand(1); in LowerFixedLengthConcatVectorsToSVE() local
21585 SrcOp2 = convertToScalableVector(DAG, ContainerVT, SrcOp2); in LowerFixedLengthConcatVectorsToSVE()
21587 Op = DAG.getNode(AArch64ISD::SPLICE, DL, ContainerVT, Pg, SrcOp1, SrcOp2); in LowerFixedLengthConcatVectorsToSVE()
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