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Searched refs:SrcC (Results 1 – 9 of 9) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Linker/
H A DLinkModules.cpp74 bool getComdatResult(const Comdat *SrcC, Comdat::SelectionKind &SK,
219 bool ModuleLinker::getComdatResult(const Comdat *SrcC, in getComdatResult() argument
223 Comdat::SelectionKind SSK = SrcC->getSelectionKind(); in getComdatResult()
224 StringRef ComdatName = SrcC->getName(); in getComdatResult()
/llvm-project-15.0.7/llvm/lib/Target/ARC/Disassembler/
H A DARCDisassembler.cpp232 unsigned SrcC, DstB, LImm; in DecodeStLImmInstruction() local
238 SrcC = decodeCField(Insn); in DecodeStLImmInstruction()
239 DecodeGPR32RegisterClass(Inst, SrcC, Address, Decoder); in DecodeStLImmInstruction()
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dmfma-no-register-aliasing.ll7 ; Check that Dst and SrcC of MFMA instructions reading more than 4 registers as SrcC
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstCombineIntrinsic.cpp1010 if (auto *SrcC = dyn_cast<ConstantInt>(II.getArgOperand(0))) { in instCombineIntrinsic() local
1011 uint64_t Src = SrcC->getZExtValue(); in instCombineIntrinsic()
1054 if (auto *SrcC = dyn_cast<ConstantInt>(II.getArgOperand(0))) { in instCombineIntrinsic() local
1055 uint64_t Src = SrcC->getZExtValue(); in instCombineIntrinsic()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonConstPropagation.cpp315 virtual bool evaluate(const RegisterSubReg &R, const LatticeCell &SrcC,
670 LatticeCell SrcC; in visitPHI() local
671 bool Eval = MCE.evaluate(UseR, Cells.get(UseR.Reg), SrcC); in visitPHI()
673 << printReg(UseR.Reg, &MCE.TRI, UseR.SubReg) << SrcC in visitPHI()
675 Changed |= Eval ? DefC.meet(SrcC) in visitPHI()
1847 bool evaluate(const RegisterSubReg &R, const LatticeCell &SrcC,
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.cpp2495 const MachineOperand *SrcC = in checkMAIVALUHazards() local
2497 assert(SrcC); in checkMAIVALUHazards()
2498 if (!SrcC->isReg() || !TRI.regsOverlap(SrcC->getReg(), Reg)) in checkMAIVALUHazards()
H A DVOP3PInstructions.td457 // Dst and SrcC cannot partially overlap if SrcC/Dst is bigger than 4 VGPRs.
H A DAMDGPU.td195 "MFMA cannot use inline literal as SrcC"
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGBuiltin.cpp18143 Address SrcC = EmitPointerWithAlignment(E->getArg(3)); in EmitNVPTXBuiltinExpr() local
18193 SrcC.getElementType(), in EmitNVPTXBuiltinExpr()
18194 Builder.CreateGEP(SrcC.getElementType(), SrcC.getPointer(), in EmitNVPTXBuiltinExpr()