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Searched refs:Sra (Results 1 – 3 of 3) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonPatterns.td363 def Add: pf2<add>; def And: pf2<and>; def Sra: pf2<sra>;
1073 def: OpR_RI_pat<S2_asr_i_r, Sra, i32, I32, u5_0ImmPred>;
1076 def: OpR_RI_pat<S2_asr_i_p, Sra, i64, I64, u6_0ImmPred>;
1079 def: OpR_RI_pat<S2_asr_i_vh, Sra, v4i16, V4I16, u4_0ImmPred>;
1082 def: OpR_RI_pat<S2_asr_i_vh, Sra, v2i32, V2I32, u5_0ImmPred>;
1086 def: OpR_RR_pat<S2_asr_r_r, Sra, i32, I32, I32>;
1089 def: OpR_RR_pat<S2_asr_r_p, Sra, i64, I64, I32>;
1239 def: AccRRR_pat<S2_asr_r_r_acc, Add, Su<Sra>, I32, I32, I32>;
1240 def: AccRRR_pat<S2_asr_r_r_nac, Sub, Su<Sra>, I32, I32, I32>;
1241 def: AccRRR_pat<S2_asr_r_r_and, And, Su<Sra>, I32, I32, I32>;
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp4415 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Add, C1); in visitSDIVLike() local
4416 AddToWorklist(Sra.getNode()); in visitSDIVLike()
4425 Sra = DAG.getSelect(DL, VT, IsOneOrAllOnes, N0, Sra); in visitSDIVLike()
4430 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, Zero, Sra); in visitSDIVLike()
4434 SDValue Res = DAG.getSelect(DL, VT, IsNeg, Sub, Sra); in visitSDIVLike()
10128 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, X, ShAmtC); in foldSelectOfConstantsUsingSra() local
10129 return DAG.getNode(ISD::OR, DL, VT, Sra, C1); in foldSelectOfConstantsUsingSra()
10136 return DAG.getNode(ISD::AND, DL, VT, Sra, C1); in foldSelectOfConstantsUsingSra()
10312 return DAG.getNode(ISD::AND, DL, VT, Sra, N1); in foldVSelectToSignBitSplatMask()
10320 return DAG.getNode(ISD::OR, DL, VT, Sra, N2); in foldVSelectToSignBitSplatMask()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp28905 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, X, ShiftAmt); in LowerADDSAT_SUBSAT() local
28906 return DAG.getNode(ISD::AND, DL, VT, Xor, Sra); in LowerADDSAT_SUBSAT()
47648 SDValue Sra = in combineAndMaskToShift() local
47651 return DAG.getNode(X86ISD::ANDNP, DL, VT, Sra, Y); in combineAndMaskToShift()