Searched refs:SplitVT (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 6716 EVT SplitVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, CmpElements); in LowerVSETCC() local
6717 SDValue CastOp0 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op0); in LowerVSETCC()
6718 SDValue CastOp1 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op1); in LowerVSETCC()
6719 SDValue Cmp = DAG.getNode(ISD::SETCC, dl, SplitVT, CastOp0, CastOp1, in LowerVSETCC()
6721 SDValue Reversed = DAG.getNode(ARMISD::VREV64, dl, SplitVT, Cmp); in LowerVSETCC()
6722 SDValue Merged = DAG.getNode(ISD::AND, dl, SplitVT, Cmp, Reversed); in LowerVSETCC()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 7856 EVT SplitVT = in LowerTRUNCATEVector() local
7858 unsigned SplitNumElts = SplitVT.getVectorNumElements(); in LowerTRUNCATEVector()
7859 Op1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, N1, in LowerTRUNCATEVector()
7861 Op2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, N1, in LowerTRUNCATEVector()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 20575 EVT SplitVT = EVT::getVectorVT(*DAG.getContext(), in reduceBuildVecToShuffle() local
20577 if (TLI.isTypeLegal(SplitVT) && in reduceBuildVecToShuffle()
20578 SplitSize + SplitVT.getVectorNumElements() <= in reduceBuildVecToShuffle()
20580 SDValue VecIn2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, Vec, in reduceBuildVecToShuffle()
20582 SDValue VecIn1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, Vec, in reduceBuildVecToShuffle()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 16591 MVT SplitVT = MVT::getVectorVT(ScalarVT, SplitNumElements); in splitAndLowerShuffle() local
16598 return std::make_pair(DAG.getBitcast(SplitVT, LoV), in splitAndLowerShuffle()
16599 DAG.getBitcast(SplitVT, HiV)); in splitAndLowerShuffle()
16637 return DAG.getUNDEF(SplitVT); in splitAndLowerShuffle()
16639 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask); in splitAndLowerShuffle()
16641 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask); in splitAndLowerShuffle()
16646 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask); in splitAndLowerShuffle()
16656 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask); in splitAndLowerShuffle()
16664 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask); in splitAndLowerShuffle()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 13397 EVT SplitVT = in LowerSVEStructLoad() local
13400 assert(isTypeLegal(SplitVT)); in LowerSVEStructLoad()
13402 SmallVector<EVT, 5> VTs(N, SplitVT); in LowerSVEStructLoad()
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