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Searched refs:Spills (Results 1 – 9 of 9) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DLiveInterval.cpp1141 OS << ' ' << Spills[I]; in print()
1221 if (!Spills.empty() && coalescable(Spills.back(), Seg)) { in add()
1222 Seg.start = Spills.back().start; in add()
1223 Seg.end = std::max(Spills.back().end, Seg.end); in add()
1224 Spills.pop_back(); in add()
1244 Spills.push_back(Seg); in add()
1255 LiveRange::iterator SpillSrc = Spills.end(); in mergeSpills()
1269 Spills.erase(SpillSrc, Spills.end()); in mergeSpills()
1281 if (Spills.empty()) { in flush()
1289 if (GapSize < Spills.size()) { in flush()
[all …]
H A DRegAllocGreedy.h396 unsigned Spills = 0; member
406 return !(Reloads || FoldedReloads || Spills || FoldedSpills || in isEmpty()
414 Spills += other.Spills; in add()
H A DInlineSpiller.cpp121 SmallPtrSet<MachineInstr *, 16> &Spills,
126 MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills,
133 SmallPtrSet<MachineInstr *, 16> &Spills,
1291 SmallPtrSet<MachineInstr *, 16> &Spills, in rmRedundantSpills() argument
1297 for (auto *const CurrentSpill : Spills) { in rmRedundantSpills()
1313 Spills.erase(SpillToRm); in rmRedundantSpills()
1323 MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills, in getVisitOrders() argument
1346 for (auto *const Spill : Spills) { in getVisitOrders()
1408 SmallPtrSet<MachineInstr *, 16> &Spills, in runHoistSpills() argument
1422 rmRedundantSpills(Spills, SpillsToRm, SpillBBToSpill); in runHoistSpills()
[all …]
H A DRegAllocGreedy.cpp2329 if (Spills) { in report()
2330 R << NV("NumSpills", Spills) << " spills "; in report()
2386 ++Stats.Spills; in computeStats()
2427 Stats.SpillsCost = RelFreq * Stats.Spills; in computeStats()
/llvm-project-15.0.7/llvm/lib/Transforms/Coroutines/
H A DCoroFrame.cpp316 SpillInfo Spills; member
323 for (const auto &P : Spills) in getAllDefs()
400 for (const auto &E : Spills) { in dumpSpills()
588 for (auto &S : Spills) in updateLayoutIndex()
1183 for (auto &S : FrameData.Spills) { in buildFrameType()
1609 for (auto const &E : FrameData.Spills) { in insertSpills()
2027 for (const auto &E : Spills) { in rewriteMaterializableInstructions()
2706 SpillInfo Spills; in buildCoroutineFrame() local
2716 if (Spills.empty()) in buildCoroutineFrame()
2723 Spills.clear(); in buildCoroutineFrame()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dx86-32-intrcc.ll10 ; Spills eax, putting original esp at +4.
30 ; Spills eax and ecx, putting original esp at +8. Stack is adjusted up another 4 bytes
H A Dx86-64-intrcc.ll9 ; Spills rax, putting original esp at +8.
29 ; Spills rax and rcx, putting original rsp at +16. Stack is adjusted up another 8 bytes
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DLiveInterval.h939 SmallVector<LiveRange::Segment, 16> Spills; variable
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstructions.td686 // that switch the VGPR indexing mode. Spills to accvgprs could be effected by