Searched refs:Sn (Results 1 – 6 of 6) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstrVFP.td | 1162 bits<5> Sn; 1165 let Inst{19-16} = Sn{4-1}; 1166 let Inst{7} = Sn{0}; 1185 bits<5> Sn; 1190 let Inst{7} = Sn{0}; 1341 bits<5> Sn; 1345 let Inst{7} = Sn{0}; 1362 bits<5> Sn; 1367 let Inst{7} = Sn{0}; 1376 def : FPRegs16Pat<(arm_vmovrh (f16 HPR:$Sn)), (VMOVRH (f16 HPR:$Sn))>; [all …]
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| H A D | ARMInstrFormats.td | 1929 bits<5> Sn; 1935 let Inst{19-16} = Sn{4-1}; 1936 let Inst{7} = Sn{0}; 1956 bits<5> Sn; 1965 let Inst{7} = Sn{0}; 1987 bits<5> Sn; 1994 let Inst{7} = Sn{0}; 2064 bits<5> Sn; 2071 let Inst{7} = Sn{0}; 2093 bits<5> Sn; [all …]
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| /llvm-project-15.0.7/llvm/tools/llvm-ml/ |
| H A D | Opts.td | 115 def listing_without_symbols : UnsupportedFlag<"Sn">, HelpText<"">;
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 782 SDValue Sn, Sm; in buildHvxVectorReg() local 788 Sn = DAG.getConstant(Rn, dl, MVT::i32); in buildHvxVectorReg() 789 HalfV0 = DAG.getNode(HexagonISD::VROR, dl, VecTy, {N, Sn}); in buildHvxVectorReg() 805 Sn = DAG.getConstant(Rn+HwLen/2, dl, MVT::i32); in buildHvxVectorReg() 807 HalfV0 = DAG.getNode(HexagonISD::VROR, dl, VecTy, {N, Sn}); in buildHvxVectorReg()
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| /llvm-project-15.0.7/lld/MachO/ |
| H A D | Options.td | 1062 def Sn : Flag<["-"], "Sn">,
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | SVEInstrFormats.td | 1199 def : InstAlias<"mov $Zd, $Sn", 1200 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, FPR32asZPR:$Sn, 0), 2>;
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