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Searched refs:Sm (Results 1 – 5 of 5) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrVFP.td712 bits<5> Sm;
823 bits<5> Sm;
827 let Inst{5} = Sm{0};
869 bits<5> Sm;
873 let Inst{5} = Sm{0};
1399 bits<5> Sm;
1418 bits<5> Sm;
1437 bits<5> Sm;
1571 bits<5> Sm;
1590 bits<5> Sm;
[all …]
H A DARMInstrFormats.td1869 bits<5> Sm;
1873 let Inst{5} = Sm{0};
1894 bits<5> Sm;
1900 let Inst{5} = Sm{0};
1930 bits<5> Sm;
1957 bits<5> Sm;
1988 bits<5> Sm;
2008 bits<5> Sm;
2036 bits<5> Sm;
2065 bits<5> Sm;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVVMReflect.cpp56 explicit NVVMReflect(unsigned int Sm) : FunctionPass(ID), SmVersion(Sm) { in NVVMReflect() argument
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp782 SDValue Sn, Sm; in buildHvxVectorReg() local
795 Sm = DAG.getConstant(Rm, dl, MVT::i32); in buildHvxVectorReg()
796 HalfV1 = DAG.getNode(HexagonISD::VROR, dl, VecTy, {M, Sm}); in buildHvxVectorReg()
806 Sm = DAG.getConstant(Rm, dl, MVT::i32); in buildHvxVectorReg()
808 HalfV1 = DAG.getNode(HexagonISD::VROR, dl, VecTy, {M, Sm}); in buildHvxVectorReg()
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp8240 const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(2).getReg()); in validateInstruction() local
8242 if (Sm1 != Sm + 1) in validateInstruction()
8249 const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(0).getReg()); in validateInstruction() local
8251 if (Sm1 != Sm + 1) in validateInstruction()