| /llvm-project-15.0.7/flang/lib/Optimizer/CodeGen/ |
| H A D | PreCGRewrite.cpp | 47 fir::ShiftOp shift) { in populateShift()
173 mlir::dyn_cast<fir::ShiftOp>(shapeVal.getDefiningOp())) in matchAndRewrite()
232 mlir::dyn_cast<fir::ShiftOp>(shapeVal.getDefiningOp())) in matchAndRewrite()
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| H A D | CodeGen.cpp | 3366 struct ShiftOpConversion : public MustBeDeadConversion<fir::ShiftOp> {
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| /llvm-project-15.0.7/flang/include/flang/Optimizer/Builder/ |
| H A D | Factory.h | 171 if (auto shOp = mlir::dyn_cast<fir::ShiftOp>(shapeOp)) { in getOrigins()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 773 unsigned ShiftOp = MI->getOperand(OpNum).getImm(); in printShiftImmOperand() local
774 bool isASR = (ShiftOp & (1 << 5)) != 0; in printShiftImmOperand()
775 unsigned Amt = ShiftOp & 0x1f; in printShiftImmOperand()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 895 unsigned ShiftOp; in PromoteIntRes_ADDSUBSHLSAT() local
900 ShiftOp = ISD::SRA; in PromoteIntRes_ADDSUBSHLSAT()
903 ShiftOp = ISD::SRL; in PromoteIntRes_ADDSUBSHLSAT()
921 return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount); in PromoteIntRes_ADDSUBSHLSAT()
966 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL; in PromoteIntRes_MULFIX() local
967 return DAG.getNode(ShiftOp, dl, PromotedType, Result, in PromoteIntRes_MULFIX()
4193 SDValue ShiftOp = N->getOperand(1); in ExpandIntRes_Shift() local
4195 if (ShiftOp.getValueType() != ShiftTy) in ExpandIntRes_Shift()
4196 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); in ExpandIntRes_Shift()
4198 SDValue Ops[] = { LHSL, LHSH, ShiftOp }; in ExpandIntRes_Shift()
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| H A D | DAGCombiner.cpp | 2375 ShiftOp.getOpcode() != ISD::SRL) in foldAddSubOfSignBit()
2379 SDValue Not = ShiftOp.getOperand(0); in foldAddSubOfSignBit()
2384 EVT VT = ShiftOp.getValueType(); in foldAddSubOfSignBit()
2385 SDValue ShAmt = ShiftOp.getOperand(1); in foldAddSubOfSignBit()
6106 if (!LogicOp.hasOneUse() || !ShiftOp.hasOneUse()) in foldLogicOfShifts()
6110 unsigned ShiftOpcode = ShiftOp.getOpcode(); in foldLogicOfShifts()
6120 SDValue X1 = ShiftOp.getOperand(0); in foldLogicOfShifts()
6121 SDValue Y = ShiftOp.getOperand(1); in foldLogicOfShifts()
7812 if (!ShiftOp) in calculateByteProvider()
7815 uint64_t BitShift = ShiftOp->getZExtValue(); in calculateByteProvider()
[all …]
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| H A D | SelectionDAGBuilder.cpp | 2836 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT); in visitBitTestCase() local
2845 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT), in visitBitTestCase()
2851 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT), in visitBitTestCase()
2856 DAG.getConstant(1, dl, VT), ShiftOp); in visitBitTestCase()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelDAGToDAG.cpp | 1908 unsigned ShiftOp = TrueOp->getSExtValue() == 1 ? ISD::SRL : ISD::SRA; in expandSelectBoolean() local
1909 Result = CurDAG->getNode(ShiftOp, DL, MVT::i32, Result, in expandSelectBoolean()
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| /llvm-project-15.0.7/flang/lib/Optimizer/Builder/ |
| H A D | MutableBox.cpp | 513 shift = builder.create<fir::ShiftOp>(loc, shiftType, newLbounds); in associateMutableBox()
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| H A D | FIRBuilder.cpp | 394 return create<fir::ShiftOp>(loc, shiftType, box.getLBounds()); in createShape()
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| /llvm-project-15.0.7/flang/lib/Optimizer/Transforms/ |
| H A D | ArrayValueCopy.cpp | 854 auto shiftOp = arrLoad.getShape().getDefiningOp<ShiftOp>(); in getOrReadExtentsAndShapeOp()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 3332 unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL; in emitINSERT_DF_VIDX() local
3377 BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1) in emitINSERT_DF_VIDX()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 7209 unsigned ShiftOp = IsSigned ? TargetOpcode::G_ASHR : TargetOpcode::G_LSHR; in lowerSMULH_UMULH() local
7212 auto Shifted = MIRBuilder.buildInstr(ShiftOp, {WideTy}, {Mul, ShiftAmt}); in lowerSMULH_UMULH()
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| /llvm-project-15.0.7/flang/lib/Optimizer/Dialect/ |
| H A D | FIROps.cpp | 3063 mlir::LogicalResult fir::ShiftOp::verify() { in verify()
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| /llvm-project-15.0.7/flang/lib/Lower/ |
| H A D | ConvertExpr.cpp | 275 if (!mlir::isa<fir::ShiftOp>(shapeVal.getDefiningOp())) {
4235 mlir::Value shiftOp = builder.create<fir::ShiftOp>(loc, shiftTy, lbs); in convertElementForUpdate()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 215 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) { in X86TargetLowering()
219 setOperationAction(ShiftOp , MVT::i8 , Custom); in X86TargetLowering()
220 setOperationAction(ShiftOp , MVT::i16 , Custom); in X86TargetLowering()
221 setOperationAction(ShiftOp , MVT::i32 , ShiftDoubleAction); in X86TargetLowering()
223 setOperationAction(ShiftOp , MVT::i64 , ShiftDoubleAction); in X86TargetLowering()
48553 SDValue ShiftOp = Shift.getOperand(0); in foldXorTruncShiftIntoCmp() local
48554 EVT ShiftOpTy = ShiftOp.getValueType(); in foldXorTruncShiftIntoCmp()
48558 SDValue Cond = DAG.getSetCC(DL, SetCCResultType, ShiftOp, in foldXorTruncShiftIntoCmp()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 17678 SDValue ShiftOp = Index.getOperand(1); in foldIndexIntoBase() local
17680 if (auto Shift = DAG.getSplatValue(ShiftOp)) in foldIndexIntoBase()
17686 Add.getOperand(0), ShiftOp); in foldIndexIntoBase()
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