| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsExpandPseudo.cpp | 181 const unsigned ShiftImm = in expandAtomicCmpSwapSubword() local
185 .addImm(ShiftImm); in expandAtomicCmpSwapSubword()
188 .addImm(ShiftImm); in expandAtomicCmpSwapSubword()
557 const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24; in expandAtomicBinOpSubword() local
560 .addImm(ShiftImm); in expandAtomicBinOpSubword()
563 .addImm(ShiftImm); in expandAtomicBinOpSubword()
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| H A D | MipsISelLowering.cpp | 1642 int64_t ShiftImm = 32 - (Size * 8); in emitSignExtendToI32InReg() local
1644 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); in emitSignExtendToI32InReg()
1645 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); in emitSignExtendToI32InReg()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 213 uint64_t ShiftImm, bool SetFlags = false,
251 unsigned RHSReg, uint64_t ShiftImm);
1325 unsigned ShiftImm; in emitAddSub_ri() local
1327 ShiftImm = 0; in emitAddSub_ri()
1329 ShiftImm = 12; in emitAddSub_ri()
1358 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm)); in emitAddSub_ri()
1375 if (ShiftImm >= RetVT.getSizeInBits()) in emitAddSub_rs()
1400 .addImm(getShifterImm(ShiftType, ShiftImm)); in emitAddSub_rs()
1416 if (ShiftImm >= 4) in emitAddSub_rx()
1444 .addImm(getArithExtendImm(ExtType, ShiftImm)); in emitAddSub_rx()
[all …]
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| H A D | AArch64ISelDAGToDAG.cpp | 1985 uint64_t ShiftImm; in isBitfieldExtractOpFromSExtInReg() local
1986 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRL, ShiftImm) && in isBitfieldExtractOpFromSExtInReg()
1987 !isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm)) in isBitfieldExtractOpFromSExtInReg()
1991 if (ShiftImm + Width > BitWidth) in isBitfieldExtractOpFromSExtInReg()
1996 Immr = ShiftImm; in isBitfieldExtractOpFromSExtInReg()
1997 Imms = ShiftImm + Width - 1; in isBitfieldExtractOpFromSExtInReg()
2122 uint64_t ShiftImm; in tryBitfieldExtractOpFromSExt() local
2124 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm)) in tryBitfieldExtractOpFromSExt()
2130 unsigned Immr = ShiftImm; in tryBitfieldExtractOpFromSExt()
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| H A D | AArch64ISelLowering.cpp | 17392 unsigned ShiftImm = N->getConstantOperandVal(1); in performVectorShiftCombine() local
17393 assert(OpScalarSize > ShiftImm && "Invalid shift imm"); in performVectorShiftCombine()
17395 APInt ShiftedOutBits = APInt::getLowBitsSet(OpScalarSize, ShiftImm); in performVectorShiftCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 873 unsigned ShiftImm; member
885 unsigned ShiftImm; member
891 unsigned ShiftImm; member
2571 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); in addRegShiftedImmOperands()
3655 Op->RegShiftedReg.ShiftImm = ShiftImm; in CreateShiftedRegister()
3667 Op->RegShiftedImm.ShiftImm = ShiftImm; in CreateShiftedImmediate()
3820 Op->Memory.ShiftImm = ShiftImm; in CreateMem()
3836 Op->PostIdxReg.ShiftImm = ShiftImm; in CreatePostIdxReg()
3975 << PostIdxReg.ShiftImm; in print()
5665 unsigned ShiftImm = 0; in parsePostIdxReg() local
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 2780 unsigned ShiftImm; in SelectShift() local
2783 ShiftImm = CI->getZExtValue(); in SelectShift()
2787 if (ShiftImm == 0 || ShiftImm >=32) in SelectShift()
2811 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); in SelectShift()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 951 unsigned Size, ShiftImm; in getMVEShiftImmOpValue() local
968 ShiftImm = MI.getOperand(OpIdx).getImm(); in getMVEShiftImmOpValue()
969 return Size + ShiftImm; in getMVEShiftImmOpValue()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 1754 Optional<int64_t> ShiftImm = getVectorShiftImm(Reg, MRI); in getVectorSHLImm() local
1755 if (!ShiftImm) in getVectorSHLImm()
1758 int64_t Imm = *ShiftImm; in getVectorSHLImm()
2291 int64_t ShiftImm; in earlySelect() local
2296 m_GOr(m_OneNonDBGUse(m_GShl(m_Reg(ShiftSrc), m_ICst(ShiftImm))), in earlySelect()
2300 if (ShiftImm > Size || ((1ULL << ShiftImm) - 1ULL) != uint64_t(MaskImm)) in earlySelect()
2303 int64_t Immr = Size - ShiftImm; in earlySelect()
2304 int64_t Imms = Size - ShiftImm - 1; in earlySelect()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 689 unsigned ShiftImm = DefMI->getOperand(3).getImm(); in simplifyCode() local
693 unsigned NewElem = (SplatImm + ShiftImm) & 0x3; in simplifyCode()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 4285 int64_t ShiftImm; in matchBitfieldExtractFromSExtInReg() local
4288 m_OneNonDBGUse(m_any_of(m_GAShr(m_Reg(ShiftSrc), m_ICst(ShiftImm)), in matchBitfieldExtractFromSExtInReg()
4289 m_GLShr(m_Reg(ShiftSrc), m_ICst(ShiftImm)))))) in matchBitfieldExtractFromSExtInReg()
4291 if (ShiftImm < 0 || ShiftImm + Width > Ty.getScalarSizeInBits()) in matchBitfieldExtractFromSExtInReg()
4295 auto Cst1 = B.buildConstant(ExtractTy, ShiftImm); in matchBitfieldExtractFromSExtInReg()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 6034 const APInt &ShiftImm = N2C->getAPIntValue(); in getNode() local
6035 return getVScale(DL, VT, MulImm << ShiftImm); in getNode()
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