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Searched refs:Shift0 (Results 1 – 2 of 2) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp675 bool Shift0 = mi_match( in selectG_BUILD_VECTOR_TRUNC() local
682 if (Shift0 && Shift1) { in selectG_BUILD_VECTOR_TRUNC()
689 } else if (Shift0) { in selectG_BUILD_VECTOR_TRUNC()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp6765 SDValue Shift0 = N0.getOperand(0); in matchBSwapHWordOrAndAnd() local
6767 if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL) in matchBSwapHWordOrAndAnd()
6769 ConstantSDNode *ShiftAmt0 = isConstOrConstSplat(Shift0.getOperand(1)); in matchBSwapHWordOrAndAnd()
6775 if (Shift0.getOperand(0) != Shift1.getOperand(0)) in matchBSwapHWordOrAndAnd()
6779 SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT, Shift0.getOperand(0)); in matchBSwapHWordOrAndAnd()