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Searched refs:Shift (Results 1 – 25 of 286) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Support/
H A DScaledNumber.cpp52 Shift && (Lower & UINT64_C(1) << (Shift - 1))); in multiply64()
64 int Shift = 0; in divide32() local
66 Shift -= Zeros; in divide32()
86 int Shift = 0; in divide64() local
88 Shift -= Zeros; in divide64()
98 Shift -= Zeros; in divide64()
111 --Shift; in divide64()
172 assert(Shift >= 0 && Shift < 64 && "undefined behavior"); in toStringAPFloat()
173 D <<= Shift; in toStringAPFloat()
215 D <<= Shift; in toString()
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H A DKnownBits.cpp173 unsigned Shift = RHS.getConstant().getZExtValue(); in shl() local
175 Known.Zero <<= Shift; in shl()
176 Known.One <<= Shift; in shl()
178 Known.Zero.setLowBits(Shift); in shl()
226 unsigned Shift = RHS.getConstant().getZExtValue(); in lshr() local
228 Known.Zero.lshrInPlace(Shift); in lshr()
229 Known.One.lshrInPlace(Shift); in lshr()
231 Known.Zero.setHighBits(Shift); in lshr()
279 unsigned Shift = RHS.getConstant().getZExtValue(); in ashr() local
281 Known.Zero.ashrInPlace(Shift); in ashr()
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/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DLEB128.h133 unsigned Shift = 0; variable
145 if ((Shift >= 64 && Slice != 0) || Slice << Shift >> Shift != Slice) {
152 Value += Slice << Shift;
153 Shift += 7;
166 unsigned Shift = 0; variable
180 if ((Shift >= 64 && Slice != (Value < 0 ? 0x7f : 0x00)) ||
181 (Shift == 63 && Slice != 0 && Slice != 0x7f)) {
188 Value |= Slice << Shift;
189 Shift += 7;
193 if (Shift < 64 && (Byte & 0x40))
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H A DScaledNumber.h89 return getRounded<DigitsT>(Digits >> Shift, Scale + Shift,
624 shiftLeft(Shift);
628 shiftRight(Shift);
837 if (Shift < 0) { in shiftLeft()
838 shiftRight(-Shift); in shiftLeft()
853 Shift -= ScaleShift; in shiftLeft()
860 Digits <<= Shift; in shiftLeft()
867 if (Shift < 0) { in shiftRight()
868 shiftLeft(-Shift); in shiftRight()
879 Shift -= ScaleShift; in shiftRight()
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H A DMathExtras.h99 T Shift = std::numeric_limits<T>::digits >> 1; in count() local
100 T Mask = std::numeric_limits<T>::max() >> Shift; in count()
101 while (Shift) { in count()
103 Val >>= Shift; in count()
104 ZeroBits |= Shift; in count()
106 Shift >>= 1; in count()
107 Mask >>= Shift; in count()
171 for (T Shift = std::numeric_limits<T>::digits >> 1; Shift; Shift >>= 1) {
172 T Tmp = Val >> Shift;
176 ZeroBits |= Shift;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ExpandImm.cpp273 Shift = (TZ / 16) * 16; in expandMOVImmSimple()
276 unsigned Imm16 = (Imm >> Shift) & Mask; in expandMOVImmSimple()
281 if (Shift == LastShift) in expandMOVImmSimple()
290 while (Shift < LastShift) { in expandMOVImmSimple()
291 Shift += 16; in expandMOVImmSimple()
292 Imm16 = (Imm >> Shift) & Mask; in expandMOVImmSimple()
311 for (unsigned Shift = 0; Shift < BitSize; Shift += 16) { in expandMOVImm() local
312 const unsigned Chunk = (Imm >> Shift) & Mask; in expandMOVImm()
354 for (unsigned Shift = 0; Shift < BitSize; Shift += 16) { in expandMOVImm() local
355 uint64_t ShiftedMask = (0xFFFFULL << Shift); in expandMOVImm()
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Utils/
H A DAMDKernelCodeTInfo.h38 #define PRINTCOMP(GetMacro, Shift) \ argument
41 (int)GetMacro(C.compute_pgm_resource_registers >> Shift); \
43 #define PARSECOMP(SetMacro, Shift) \ argument
48 C.compute_pgm_resource_registers &= ~(SetMacro(0xFFFFFFFFFFFFFFFFULL) << Shift); \
49 C.compute_pgm_resource_registers |= SetMacro(Value) << Shift; \
53 #define COMPPGM(name, aname, GetMacro, SetMacro, Shift) \ argument
54 RECORD(name, aname, PRINTCOMP(GetMacro, Shift), PARSECOMP(SetMacro, Shift))
H A DAMDGPUAsmUtils.h38 unsigned Shift; member
43 unsigned decode(unsigned Code) const { return (Code >> Shift) & Mask; } in decode()
45 unsigned encode(unsigned Val) const { return (Val & Mask) << Shift; } in encode()
47 unsigned getMask() const { return Mask << Shift; } in getMask()
/llvm-project-15.0.7/llvm/include/llvm/ADT/
H A DPointerEmbeddedInt.h44 Shift = sizeof(uintptr_t) * CHAR_BIT - Bits, enumerator
66 Value = static_cast<uintptr_t>(I) << Shift;
74 return static_cast<IntT>(static_cast<intptr_t>(Value) >> Shift);
75 return static_cast<IntT>(Value >> Shift);
97 static constexpr int NumLowBitsAvailable = T::Shift;
H A DBitfields.h166 static constexpr StorageType Mask = BP::Umax << Bitfield::Shift;
173 Packed |= StorageValue << Bitfield::Shift;
179 const StorageType StorageValue = (Packed & Mask) >> Bitfield::Shift;
227 static constexpr unsigned Shift = Offset;
230 static constexpr unsigned LastBit = Shift + Bits - 1;
231 static constexpr unsigned NextBit = Shift + Bits;
/llvm-project-15.0.7/compiler-rt/lib/gwp_asan/
H A Dstack_trace_compressor.cpp37 uint8_t Shift = 0; in varIntDecode() local
40 *Out |= (static_cast<uintptr_t>(In[i]) & 0x7f) << Shift; in varIntDecode()
45 Shift += 7; in varIntDecode()
48 if (Shift >= sizeof(uintptr_t) * 8) in varIntDecode()
/llvm-project-15.0.7/clang/lib/Format/
H A DWhitespaceManager.cpp279 int Shift = 0; in AlignTokenSequence() local
329 Shift = 0; in AlignTokenSequence()
340 Changes[i].Spaces += Shift; in AlignTokenSequence()
431 Changes[i].Spaces += Shift; in AlignTokenSequence()
435 Changes[i].Spaces += Shift; in AlignTokenSequence()
673 int Shift = 0; in AlignMacroSequence() local
677 Shift = 0; in AlignMacroSequence()
690 assert(Shift >= 0); in AlignMacroSequence()
1009 int Shift = 0; in alignTrailingComments() local
1017 if (Shift < 0) in alignTrailingComments()
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/llvm-project-15.0.7/mlir/include/mlir/Dialect/SPIRV/IR/
H A DSPIRVBitOps.td418 Shift the bits in Base left by the number of bits specified in Shift.
425 The type of each Base and Shift must be a scalar or vector of integer
426 type. Base and Shift must have the same number of components. The
430 Shift is treated as unsigned. The result is undefined if Shift is
463 Shift the bits in Base right by the number of bits specified in Shift.
471 type. Base and Shift must have the same number of components. The
475 Shift is treated as unsigned. The result is undefined if Shift is
505 Shift the bits in Base right by the number of bits specified in Shift.
513 type. Base and Shift must have the same number of components. The
517 Shift is consumed as an unsigned integer. The result is undefined if
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/llvm-project-15.0.7/libc/AOR_v20.02/math/
H A Dv_cosf.c29 #define Shift v_f32 (0x1.8p+23f) macro
52 n = v_fma_f32 (InvPi, r + HalfPi, Shift); in V_NAME()
54 n -= Shift; in V_NAME()
H A Dv_sinf.c29 #define Shift v_f32 (0x1.8p+23f) macro
52 n = v_fma_f32 (InvPi, r, Shift); in V_NAME()
54 n -= Shift; in V_NAME()
H A Dexp.c18 #define Shift __exp_data.shift macro
118 kd = eval_as_double (z + Shift); in exp_inline()
123 kd = eval_as_double (z + Shift); in exp_inline()
125 kd -= Shift; in exp_inline()
H A Dv_exp2f_1u.c24 #define Shift v_f32 (0x1.8p23f) macro
54 z = x + Shift; in V_NAME()
55 n = z - Shift; in V_NAME()
H A Dv_sin.c37 #define Shift v_f64 (0x1.8p52) macro
60 n = v_fma_f64 (InvPi, r, Shift); in V_NAME()
62 n -= Shift; in V_NAME()
H A Dv_cos.c38 #define Shift v_f64 (0x1.8p52) macro
60 n = v_fma_f64 (InvPi, r + HalfPi, Shift); in V_NAME()
62 n -= Shift; in V_NAME()
H A Dv_exp2f.c27 #define Shift v_f32 (0x1.8p23f) macro
56 z = x + Shift; in V_NAME()
57 n = z - Shift; in V_NAME()
H A Dv_expf_1u.c27 #define Shift v_f32 (0x1.8p23f) macro
56 z = v_fma_f32 (x, InvLn2, Shift); in V_NAME()
57 n = z - Shift; in V_NAME()
H A Dv_exp.c39 #define Shift v_f64 (0x1.8p+52) macro
68 z = v_fma_f64 (x, InvLn2, Shift); in V_NAME()
70 n = z - Shift; in V_NAME()
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Hexagon/
H A Dxtype_shift.txt4 # Shift by immediate
18 # Shift by immediate and accumulate
52 # Shift by immediate and add
56 # Shift by immediate and logical
98 # Shift right by immediate with rounding
104 # Shift left by immediate with saturation
108 # Shift by register
128 # Shift by register and accumulate
162 # Shift by register and logical
204 # Shift by register with saturation
/llvm-project-15.0.7/llvm/lib/Transforms/Utils/
H A DIntegerDivision.cpp35 ConstantInt *Shift; in generateSignedRemainderCode() local
38 Shift = Builder.getInt64(63); in generateSignedRemainderCode()
41 Shift = Builder.getInt32(31); in generateSignedRemainderCode()
56 Value *DividendSign = Builder.CreateAShr(Dividend, Shift); in generateSignedRemainderCode()
57 Value *DivisorSign = Builder.CreateAShr(Divisor, Shift); in generateSignedRemainderCode()
107 ConstantInt *Shift; in generateSignedDivisionCode() local
110 Shift = Builder.getInt64(63); in generateSignedDivisionCode()
113 Shift = Builder.getInt32(31); in generateSignedDivisionCode()
129 Value *Tmp = Builder.CreateAShr(Dividend, Shift); in generateSignedDivisionCode()
130 Value *Tmp1 = Builder.CreateAShr(Divisor, Shift); in generateSignedDivisionCode()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h811 for (int Shift = 0; Shift <= RegWidth - 16; Shift += 16) in isAnyMOVZMovAlias() local
812 if ((Value & ~(0xffffULL << Shift)) == 0) in isAnyMOVZMovAlias()
818 inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth) { in isMOVZMovAlias() argument
823 if (Value == 0 && Shift != 0) in isMOVZMovAlias()
826 return (Value & ~(0xffffULL << Shift)) == 0; in isMOVZMovAlias()
829 inline static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth) { in isMOVNMovAlias() argument
838 return isMOVZMovAlias(Value, Shift, RegWidth); in isMOVNMovAlias()

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