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Searched refs:ShOpc (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp53 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, in printRegImmShift() argument
55 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) in printRegImmShift()
59 assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0"); in printRegImmShift()
60 O << getShiftOpcStr(ShOpc); in printRegImmShift()
62 if (ShOpc != ARM_AM::rrx) { in printRegImmShift()
406 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand() local
407 O << ", " << ARM_AM::getShiftOpcStr(ShOpc); in printSORegRegOperand()
408 if (ShOpc == ARM_AM::rrx) in printSORegRegOperand()
H A DARMMCCodeEmitter.cpp246 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { in getShiftOp()
247 switch (ShOpc) { in getShiftOp()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp5895 unsigned ShOpc = IsLeft ? TargetOpcode::G_SHL : TargetOpcode::G_LSHR; in lowerRotate() local
5905 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); in lowerRotate()
5914 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); in lowerRotate()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp233 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); in convertToThreeAddress() local
234 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); in convertToThreeAddress()
H A DARMISelDAGToDAG.cpp3378 SDValue ShOpc = in tryV6T2BitfieldExtractOp() local
3381 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc, in tryV6T2BitfieldExtractOp()
H A DARMISelLowering.cpp6611 unsigned ShOpc = N->getOpcode(); in Expand64BitShift() local
6627 if (ShOpc == ISD::SRL) { in Expand64BitShift()
6636 } else if (ShOpc == ISD::SRA) in Expand64BitShift()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp7247 unsigned ShOpc = IsLeft ? ISD::SHL : ISD::SRL; in expandROT() local
7257 ShVal = DAG.getNode(ShOpc, DL, VT, Op0, ShAmt); in expandROT()
7265 ShVal = DAG.getNode(ShOpc, DL, VT, Op0, ShAmt); in expandROT()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp30100 unsigned ShOpc = ConstantAmt ? Opc : X86OpcV; in LowerShift() local
30101 SDValue R0 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt0)); in LowerShift()
30102 SDValue R1 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt1)); in LowerShift()
30103 SDValue R2 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt2)); in LowerShift()
30104 SDValue R3 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt3)); in LowerShift()