| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAddressingModes.h | 112 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc() argument
113 return ShOp | (Imm << 3); in getSORegOpc()
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| H A D | ARMMCCodeEmitter.cpp | 1259 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue() local
1260 unsigned SBits = getShiftOp(ShOp); in getLdStSORegOpValue()
1297 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); in getAddrMode2OffsetOpValue() local
1299 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5] in getAddrMode2OffsetOpValue()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstrNEON.td | 2646 ValueType Ty, SDNode ShOp>
2651 (Ty (ShOp (Ty DPR:$Vn),
2663 (Ty (ShOp (Ty DPR:$Vn),
2867 (Ty (ShOp (Ty DPR:$src1),
2880 (Ty (ShOp (Ty DPR:$src1),
3248 ValueType Ty, SDNode ShOp>
3269 ValueType Ty,SDNode ShOp>
3276 ValueType Ty,SDNode ShOp>
3534 v4i32, v2i32, ShOp>;
3834 mul, ShOp>;
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 2219 CreateShiftExtend(AArch64_AM::ShiftExtendType ShOp, unsigned Val, in CreateShiftExtend() argument
2222 Op->ShiftExtend.Type = ShOp; in CreateShiftExtend()
3196 AArch64_AM::ShiftExtendType ShOp = in tryParseOptionalShiftExtend() local
3213 if (ShOp == AArch64_AM::InvalidShiftExtend) in tryParseOptionalShiftExtend()
3222 if (ShOp == AArch64_AM::LSL || ShOp == AArch64_AM::LSR || in tryParseOptionalShiftExtend()
3223 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR || in tryParseOptionalShiftExtend()
3224 ShOp == AArch64_AM::MSL) { in tryParseOptionalShiftExtend()
3233 AArch64Operand::CreateShiftExtend(ShOp, 0, false, S, E, getContext())); in tryParseOptionalShiftExtend()
3258 ShOp, MCE->getValue(), true, S, E, getContext())); in tryParseOptionalShiftExtend()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 2157 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; in DecodeSORegMemOperand() local
2160 ShOp = ARM_AM::lsl; in DecodeSORegMemOperand()
2163 ShOp = ARM_AM::lsr; in DecodeSORegMemOperand()
2166 ShOp = ARM_AM::asr; in DecodeSORegMemOperand()
2169 ShOp = ARM_AM::ror; in DecodeSORegMemOperand()
2173 if (ShOp == ARM_AM::ror && imm == 0) in DecodeSORegMemOperand()
2174 ShOp = ARM_AM::rrx; in DecodeSORegMemOperand()
2182 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); in DecodeSORegMemOperand()
2184 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); in DecodeSORegMemOperand()
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| /llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCompares.cpp | 1580 Value *ShOp; in foldICmpTruncConstant() local
1584 match(X, m_Shr(m_Value(ShOp), m_APInt(ShAmtC))) && in foldICmpTruncConstant()
1587 ? new ICmpInst(ICmpInst::ICMP_SLT, ShOp, in foldICmpTruncConstant()
1589 : new ICmpInst(ICmpInst::ICMP_SGT, ShOp, in foldICmpTruncConstant()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 5377 SDValue ShOp = N0.getOperand(1); in hoistLogicOpWithSameOpcodeHands() local
5378 if (LogicOpcode == ISD::XOR && !ShOp.isUndef()) in hoistLogicOpWithSameOpcodeHands()
5379 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations); in hoistLogicOpWithSameOpcodeHands()
5382 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) { in hoistLogicOpWithSameOpcodeHands()
5385 return DAG.getVectorShuffle(VT, DL, Logic, ShOp, SVN0->getMask()); in hoistLogicOpWithSameOpcodeHands()
5390 ShOp = N0.getOperand(0); in hoistLogicOpWithSameOpcodeHands()
5391 if (LogicOpcode == ISD::XOR && !ShOp.isUndef()) in hoistLogicOpWithSameOpcodeHands()
5392 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations); in hoistLogicOpWithSameOpcodeHands()
5395 if (N0.getOperand(0) == N1.getOperand(0) && ShOp.getNode()) { in hoistLogicOpWithSameOpcodeHands()
5398 return DAG.getVectorShuffle(VT, DL, ShOp, Logic, SVN0->getMask()); in hoistLogicOpWithSameOpcodeHands()
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| H A D | LegalizeVectorTypes.cpp | 4492 SDValue ShOp = N->getOperand(1); in WidenVecRes_POWI() local
4493 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp); in WidenVecRes_POWI()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatterns.td | 1274 class OpshIRI_pat<InstHexagon MI, PatFrag Op, PatFrag ShOp,
1276 : Pat<(Op anyimm:$u8, (ShOp RegPred:$Rs, ImmPred:$U5)),
|