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Searched refs:Sh (Results 1 – 12 of 12) sorted by relevance

/llvm-project-15.0.7/clang/include/clang/Basic/
H A Darm_fp16.td20 def VNEGSH : SInst<"vneg", "11", "Sh">;
24 def FSQRTSH : SInst<"vsqrt", "11", "Sh">;
28 def SCALAR_FRECPEH : IInst<"vrecpe", "11", "Sh">;
31 def SCALAR_FRECPXH : IInst<"vrecpx", "11", "Sh">;
37 def FRINTZ_S64H : SInst<"vrnd", "11", "Sh">;
38 def FRINTA_S64H : SInst<"vrnda", "11", "Sh">;
39 def FRINTI_S64H : SInst<"vrndi", "11", "Sh">;
40 def FRINTM_S64H : SInst<"vrndm", "11", "Sh">;
41 def FRINTN_S64H : SInst<"vrndn", "11", "Sh">;
42 def FRINTP_S64H : SInst<"vrndp", "11", "Sh">;
[all …]
H A Darm_neon.td1817 def SCALAR_FMLA_LANEH : IInst<"vfma_lane", "111.I", "Sh">;
1818 def SCALAR_FMLA_LANEQH : IInst<"vfma_laneq", "111QI", "Sh"> {
1830 def SCALAR_FMLS_LANEH : IOpInst<"vfms_lane", "111.I", "Sh", OP_FMS_LN>;
1831 def SCALAR_FMLS_LANEQH : IOpInst<"vfms_laneq", "111QI", "Sh", OP_FMS_LNQ> {
1840 def SCALAR_FMUL_LANEH : IOpInst<"vmul_lane", "11.I", "Sh", OP_SCALAR_MUL_LN>;
1841 def SCALAR_FMUL_LANEQH : IOpInst<"vmul_laneq", "11QI", "Sh", OP_SCALAR_MUL_LN> {
1852 def SCALAR_FMULX_LANEH : IInst<"vmulx_lane", "11.I", "Sh">;
1853 def SCALAR_FMULX_LANEQH : IInst<"vmulx_laneq", "11QI", "Sh"> {
1871 def SCALAR_VDUP_LANEH : IInst<"vdup_lane", "1.I", "Sh">;
1872 def SCALAR_VDUP_LANEQH : IInst<"vdup_laneq", "1QI", "Sh"> {
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DBitTracker.cpp257 Sh = Sh % W; in rol()
258 if (Sh == 0) in rol()
261 RegisterCell Tmp(W-Sh); in rol()
519 uint16_t Sh) const { in eASL()
522 Res.rol(Sh); in eASL()
528 uint16_t Sh) const { in eLSR()
530 assert(Sh <= W); in eLSR()
532 Res.rol(W-Sh); in eLSR()
538 uint16_t Sh) const { in eASR()
540 assert(Sh <= W); in eASR()
[all …]
H A DBitTracker.h319 RegisterCell &rol(uint16_t Sh); // Rotate left.
427 RegisterCell eASL(const RegisterCell &A1, uint16_t Sh) const;
428 RegisterCell eLSR(const RegisterCell &A1, uint16_t Sh) const;
429 RegisterCell eASR(const RegisterCell &A1, uint16_t Sh) const;
/llvm-project-15.0.7/lldb/test/API/functionalities/postmortem/FreeBSDKernel/tools/
H A Dlibfbsdvmcore-hacks.patch252 .Sh SEE ALSO
258 .Sh BUGS
279 .Sh NAME
285 .Sh LIBRARY
287 .Sh SYNOPSIS
293 .Sh DESCRIPTION
314 .Sh RETURN VALUES
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombinePHI.cpp1031 PHIUsageRecord(unsigned Pn, unsigned Sh, Instruction *User) in PHIUsageRecord()
1032 : PHIId(Pn), Shift(Sh), Inst(User) {} in PHIUsageRecord()
1049 LoweredPHIRecord(PHINode *Phi, unsigned Sh, Type *Ty) in LoweredPHIRecord()
1050 : PN(Phi), Shift(Sh), Width(Ty->getPrimitiveSizeInBits()) {} in LoweredPHIRecord()
1053 LoweredPHIRecord(PHINode *Phi, unsigned Sh) : PN(Phi), Shift(Sh), Width(0) {} in LoweredPHIRecord()
H A DInstCombineCasts.cpp1006 Value *Sh = ConstantInt::get(In->getType(), in transformZExtICmp() local
1008 In = Builder.CreateLShr(In, Sh, In->getName() + ".lobit"); in transformZExtICmp()
1375 Value *Sh = ConstantInt::get(Op0->getType(), in transformSExtICmp() local
1377 Value *In = Builder.CreateAShr(Op0, Sh, Op0->getName() + ".lobit"); in transformSExtICmp()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp764 if (ConstantSDNode *Sh = in SelectLdStSOReg() local
766 ShAmt = Sh->getZExtValue(); in SelectLdStSOReg()
786 if (ConstantSDNode *Sh = in SelectLdStSOReg() local
788 ShAmt = Sh->getZExtValue(); in SelectLdStSOReg()
839 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) { in SelectAddrMode2OffsetReg() local
840 ShAmt = Sh->getZExtValue(); in SelectAddrMode2OffsetReg()
1513 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) { in SelectT2AddrModeSoReg() local
1514 ShAmt = Sh->getZExtValue(); in SelectT2AddrModeSoReg()
/llvm-project-15.0.7/lldb/test/API/functionalities/postmortem/FreeBSDKernel/
H A Dvmcore-amd64-minidump.bz21minidump FreeBSD/
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp3814 SDValue Sh = in ExpandNode() local
3818 VT.getScalarType(), Ex, Sh)); in ExpandNode()
H A DDAGCombiner.cpp4082 SDValue Sh, Y; in visitMUL() local
4087 Sh = N0; Y = N1; in visitMUL()
4091 Sh = N1; Y = N0; in visitMUL()
4094 if (Sh.getNode()) { in visitMUL()
4095 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, Sh.getOperand(0), Y); in visitMUL()
4096 return DAG.getNode(ISD::SHL, DL, VT, Mul, Sh.getOperand(1)); in visitMUL()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp11385 if (SDValue Sh = buildFromShuffleMostly(Op, DAG)) in LowerBUILD_VECTOR() local
11386 return Sh; in LowerBUILD_VECTOR()