| /llvm-project-15.0.7/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchFloat32InstrInfo.td | 147 /// Setcc
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| H A D | LoongArchFloat64InstrInfo.td | 153 /// Setcc
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| H A D | LoongArchInstrInfo.td | 689 /// Setcc
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 560 bool tryVPTESTM(SDNode *Root, SDValue Setcc, SDValue Mask);
4524 bool X86DAGToDAGISel::tryVPTESTM(SDNode *Root, SDValue Setcc, in tryVPTESTM() argument
4527 assert(Setcc.getSimpleValueType().getVectorElementType() == MVT::i1 && in tryVPTESTM()
4531 ISD::CondCode CC = cast<CondCodeSDNode>(Setcc.getOperand(2))->get(); in tryVPTESTM()
4535 SDValue SetccOp0 = Setcc.getOperand(0); in tryVPTESTM()
4536 SDValue SetccOp1 = Setcc.getOperand(1); in tryVPTESTM()
4623 MVT ResVT = Setcc.getSimpleValueType(); in tryVPTESTM()
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| H A D | X86ScheduleBtVer2.td | 230 def : WriteRes<WriteSETCC, [JALU01]>; // Setcc.
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| H A D | X86ScheduleBdVer2.td | 500 def : WriteRes<WriteSETCC, [PdEX01]>; // Setcc.
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| H A D | X86SchedSandyBridge.td | 179 def : WriteRes<WriteSETCC, [SBPort05]>; // Setcc.
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| H A D | X86SchedSkylakeClient.td | 167 def : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc.
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| H A D | X86SchedBroadwell.td | 184 def : WriteRes<WriteSETCC, [BWPort06]>; // Setcc.
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| H A D | X86SchedHaswell.td | 186 def : WriteRes<WriteSETCC, [HWPort06]>; // Setcc.
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| H A D | X86SchedSkylakeServer.td | 168 def : WriteRes<WriteSETCC, [SKXPort06]>; // Setcc.
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| H A D | X86SchedIceLake.td | 176 def : WriteRes<WriteSETCC, [ICXPort06]>; // Setcc.
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| H A D | X86ISelLowering.cpp | 43242 SDValue Setcc = DAG.getSetCC(DL, SetccVT, Movmsk, CmpC, CondCode); in combinePredicateReduction() local
43243 SDValue Zext = DAG.getZExtOrTrunc(Setcc, DL, ExtractVT); in combinePredicateReduction()
51677 SDValue Setcc = DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, N0->getOperand(0), in combineSext() local
51680 DCI.CombineTo(N, Setcc); in combineSext()
51684 N0.getValueType(), Setcc); in combineSext()
51834 SDValue Setcc = DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, N0->getOperand(0), in combineZext() local
51837 DCI.CombineTo(N, Setcc); in combineZext()
51841 N0.getValueType(), Setcc); in combineZext()
52195 SDValue Setcc = DAG.getSetCC(DL, OpVT, LHS, RHS, CC); in combineSetCC() local
52196 return DAG.getNode(ISD::TRUNCATE, DL, VT, Setcc); in combineSetCC()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoZfh.td | 309 /// Setcc
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| H A D | RISCVInstrInfoD.td | 307 /// Setcc
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| H A D | RISCVInstrInfoF.td | 537 /// Setcc
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| H A D | RISCVInstrInfo.td | 1253 /// Setcc
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| H A D | RISCVISelLowering.cpp | 1874 SDValue Setcc = DAG.getSetCC(DL, SetccVT, Abs, MaxValNode, ISD::SETOLT); in lowerFTRUNC_FCEIL_FFLOOR() local
1875 return DAG.getSelect(DL, VT, Setcc, Truncated, Src); in lowerFTRUNC_FCEIL_FFLOOR()
1926 SDValue Setcc = DAG.getSetCC(DL, SetccVT, Abs, MaxValNode, ISD::SETOLT); in lowerFROUND() local
1927 return DAG.getSelect(DL, VT, Setcc, Truncated, Src); in lowerFROUND()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 6058 SDValue Setcc = DAG.getSetCC(DL, CCVT, NewAnd, Zero, ISD::SETEQ); in combineShiftAnd1ToBitTest() local
6059 return DAG.getZExtOrTrunc(Setcc, DL, VT); in combineShiftAnd1ToBitTest()
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