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Searched refs:Sequential (Results 1 – 25 of 25) sorted by relevance

/llvm-project-15.0.7/mlir/lib/Dialect/GPU/Transforms/
H A DParallelLoopMapper.cpp35 if (processor != gpu::Processor::Sequential && in setMappingAttr()
48 enum MappingLevel { MapGrid = 0, MapBlock = 1, Sequential = 2 }; enumerator
56 if (mappingLevel < Sequential) { in operator ++()
70 if (dimension >= kNumHardwareIds || level == Sequential) in getHardwareIdForMapping()
71 return Processor::Sequential; in getHardwareIdForMapping()
82 return Processor::Sequential; in getHardwareIdForMapping()
94 return Processor::Sequential; in getHardwareIdForMapping()
98 return Processor::Sequential; in getHardwareIdForMapping()
/llvm-project-15.0.7/mlir/include/mlir/Dialect/GPU/IR/
H A DParallelLoopMapperAttr.td26 def Sequential : I64EnumAttrCase<"Sequential", 6, "sequential">;
29 BlockX, BlockY, BlockZ, ThreadX, ThreadY, ThreadZ, Sequential]> {
/llvm-project-15.0.7/flang/runtime/
H A Dconnection.h23 enum class Access { Sequential, Direct, Stream }; enumerator
28 Access access{Access::Sequential}; // ACCESS='SEQUENTIAL', 'DIRECT', 'STREAM'
H A Dunit.cpp287 if (access == Access::Sequential) { in Emit()
437 if (access == Access::Sequential) { in BeginReadingRecord()
514 if (access == Access::Sequential) { in AdvanceRecord()
H A Dio-stmt.cpp266 unit().isUnformatted = unit().access != Access::Sequential; in CompleteOperation()
1066 case Access::Sequential: in Inquire()
1211 : unit().access == Access::Sequential ? "YES" in Inquire()
H A Dio-api.cpp332 if (unit->access == Access::Sequential) { in BeginUnformattedIO()
712 open->set_access(Access::Sequential); in IONAME()
/llvm-project-15.0.7/llvm/test/MachineVerifier/
H A Dtest_vector_reductions.mir28 ; CHECK: Bad machine code: Sequential FADD/FMUL vector reduction requires a scalar 1st operand
31 ; CHECK: Bad machine code: Sequential FADD/FMUL vector reduction must have a vector 2nd operand
/llvm-project-15.0.7/flang/include/flang/Common/
H A DFortran.h53 Pending, Pos, Position, Read, Readwrite, Rec, Recl, Round, Sequential, Sign,
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td90 // Sequential vector load and shuffle.
/llvm-project-15.0.7/llvm/include/llvm/Analysis/
H A DScalarEvolution.h637 bool Sequential = false);
639 bool Sequential = false);
732 bool Sequential = false);
737 bool Sequential = false);
/llvm-project-15.0.7/mlir/include/mlir/Dialect/SCF/IR/
H A DSCFOps.td377 // Sequential context.
408 // Sequential context.
414 // Sequential context.
427 // Sequential context.
/llvm-project-15.0.7/flang/lib/Semantics/
H A Dcheck-io.cpp401 case ParseKind::Sequential: in Enter()
402 specKind = IoSpecKind::Sequential; in Enter()
/llvm-project-15.0.7/mlir/lib/Conversion/SCFToGPU/
H A DSCFToGPU.cpp352 return processor != gpu::Processor::Sequential; in isMappedToProcessor()
/llvm-project-15.0.7/flang/lib/Parser/
H A Dio-parsers.cpp472 pure(InquireSpec::CharVar::Kind::Sequential),
/llvm-project-15.0.7/mlir/test/Target/LLVMIR/Import/
H A Dbasic.ll99 ; Sequential constants.
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DScalarEvolution.cpp4210 bool Sequential) { in getUMinExpr() argument
4212 return getUMinExpr(Ops, Sequential); in getUMinExpr()
4216 bool Sequential) { in getUMinExpr() argument
4217 return Sequential ? getSequentialMinMaxExpr(scSequentialUMinExpr, Ops) in getUMinExpr()
4650 bool Sequential) { in getUMinFromMismatchedTypes() argument
4652 return getUMinFromMismatchedTypes(Ops, Sequential); in getUMinFromMismatchedTypes()
4657 bool Sequential) { in getUMinFromMismatchedTypes() argument
4678 return getUMinExpr(PromotedOps, Sequential); in getUMinFromMismatchedTypes()
/llvm-project-15.0.7/llvm/docs/
H A DAMDGPUOperandSyntax.rst85 GFX10 *Image* instructions may use special *NSA* (Non-Sequential Address) syntax for *image address…
H A DProgrammersManual.rst1489 Sequential Containers (std::vector, std::list, etc)
1809 Other Sequential Container options
2130 set-like container along with a :ref:`Sequential Container <ds_sequential>` The
H A DAMDGPUUsage.rst6187 **Sequential Consistent Atomic**
8550 **Sequential Consistent Atomic**
10969 **Sequential Consistent Atomic**
12936 **Sequential Consistent Atomic**
/llvm-project-15.0.7/llvm/unittests/Analysis/Inputs/ir2native_x86_64_model/
H A Dsaved_model.pbtxt8465 …Sequential\", \"name\": \"sequential\", \"trainable\": true, \"expects_training_arg\": true, \"dty…
/llvm-project-15.0.7/llvm/docs/Proposals/
H A DGitHubMove.rst122 - "Sequential IDs are important for LNT and llvmlab bisection tool." [MatthewsRevNum]_.
/llvm-project-15.0.7/flang/include/flang/Parser/
H A Dparse-tree.h2799 Readwrite, Round, Sequential, Sign, Stream, Status, Unformatted, Write,
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dhorizontal-sum.ll525 ; Vectorized Sequential Sum Reductions
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGBuiltin.cpp821 Sequential, enumerator
847 return {Reset, Sequential, false}; in decodeBitTestBuiltin()
849 return {Set, Sequential, false}; in decodeBitTestBuiltin()
861 return {Reset, Sequential, true}; in decodeBitTestBuiltin()
863 return {Set, Sequential, true}; in decodeBitTestBuiltin()
932 case BitTest::Sequential: return llvm::AtomicOrdering::SequentiallyConsistent; in getBitTestAtomicOrdering()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEInstrVec.td1039 // Section 8.11.8 - VSEQ (Vector Sequential Number)