| /llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSelect.cpp | 1272 Value *Sel1 = Sel0.getFalseValue(); in canonicalizeClampLike() local
1285 if (!isa<SelectInst>(Sel1)) { in canonicalizeClampLike()
1287 std::swap(X, Sel1); in canonicalizeClampLike()
1321 if (!Sel1->hasOneUse()) in canonicalizeClampLike()
1343 if (!match(Sel1, m_Select(m_Value(Cmp1), m_Value(ReplacementLow), in canonicalizeClampLike()
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonLoopIdiomRecognition.cpp | 1679 if (SelectInst *Sel1 = dyn_cast<SelectInst>(Sel->getFalseValue())) { in setupPreSimplifier() local
1680 if (Sel1->getCondition() == C) in setupPreSimplifier()
1681 return B.CreateSelect(C, Sel->getTrueValue(), Sel1->getFalseValue()); in setupPreSimplifier()
|
| /llvm-project-15.0.7/llvm/unittests/Frontend/ |
| H A D | OpenMPIRBuilderTest.cpp | 3652 SelectInst *Sel1 = dyn_cast<SelectInst>(ExtVal2->getNextNode()); in TEST_F() local
3653 EXPECT_NE(Sel1, nullptr); in TEST_F()
3654 EXPECT_EQ(Sel1->getCondition(), ExtVal2); in TEST_F()
3655 EXPECT_EQ(Sel1->getTrueValue(), Expr); in TEST_F()
3656 EXPECT_EQ(Sel1->getFalseValue(), ExtVal1); in TEST_F()
3657 StoreInst *Store1 = dyn_cast<StoreInst>(Sel1->getNextNode()); in TEST_F()
3660 EXPECT_EQ(Store1->getValueOperand(), Sel1); in TEST_F()
|
| /llvm-project-15.0.7/llvm/lib/Transforms/Utils/ |
| H A D | SimplifyLibCalls.cpp | 1209 Value *Sel1 = NullPtr; in optimizeMemChr() local
1218 Sel1 = B.CreateSelect(And, SrcPlus, NullPtr, "memchr.sel1"); in optimizeMemChr()
1225 return B.CreateSelect(And, SrcStr, Sel1, "memchr.sel2"); in optimizeMemChr()
|
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 2316 bool Sel1 = SelectVOP3PMadMixModsImpl(Src1, Src1, Src1Mods); in SelectFMAD_FMA() local
2324 if (Sel0 || Sel1 || Sel2) { in SelectFMAD_FMA()
|
| H A D | AMDGPUISelLowering.cpp | 1844 SDValue Sel1 = DAG.getSelectCC(DL, C6, Zero, Add4, Add3, ISD::SETNE); in LowerUDIVREM64() local
1845 SDValue Div = DAG.getSelectCC(DL, C3, Zero, Sel1, Mulhi3, ISD::SETNE); in LowerUDIVREM64()
|
| H A D | AMDGPULegalizerInfo.cpp | 3626 auto Sel1 = B.buildSelect( in legalizeUnsignedDIV_REM64Impl() local
3629 Sel1, MulHi3); in legalizeUnsignedDIV_REM64Impl()
|
| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 7942 SDValue Sel1; in LowerSELECT_CC() local
7952 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
7953 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
7954 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); in LowerSELECT_CC()
7956 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV); in LowerSELECT_CC()
7988 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
7989 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
7990 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); in LowerSELECT_CC()
7992 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV); in LowerSELECT_CC()
|
| /llvm-project-15.0.7/llvm/lib/IR/ |
| H A D | AutoUpgrade.cpp | 2537 Value *Sel1 = Builder.CreateAnd(CI->getArgOperand(1), NotSel); in UpgradeIntrinsicCall() local
2538 Rep = Builder.CreateOr(Sel0, Sel1); in UpgradeIntrinsicCall()
|