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Searched refs:SchedWrite (Results 1 – 25 of 35) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVSchedule.td24 def WriteNop : SchedWrite;
58 def WriteFCvtI32ToF16 : SchedWrite;
59 def WriteFCvtI32ToF32 : SchedWrite;
60 def WriteFCvtI32ToF64 : SchedWrite;
66 def WriteFCvtF16ToI32 : SchedWrite;
68 def WriteFCvtF32ToI32 : SchedWrite;
70 def WriteFCvtF64ToI32 : SchedWrite;
74 def WriteFCvtF32ToF64 : SchedWrite;
75 def WriteFCvtF64ToF32 : SchedWrite;
76 def WriteFCvtF16ToF32 : SchedWrite;
[all …]
H A DRISCVScheduleV.td14 def WriteVLDE8 : SchedWrite;
15 def WriteVLDE16 : SchedWrite;
16 def WriteVLDE32 : SchedWrite;
17 def WriteVLDE64 : SchedWrite;
18 def WriteVSTE8 : SchedWrite;
19 def WriteVSTE16 : SchedWrite;
20 def WriteVSTE32 : SchedWrite;
21 def WriteVSTE64 : SchedWrite;
23 def WriteVLDM : SchedWrite;
24 def WriteVSTM : SchedWrite;
[all …]
H A DRISCVScheduleB.td16 def WriteRotateImm : SchedWrite;
17 def WriteRotateImm32 : SchedWrite;
18 def WriteRotateReg : SchedWrite;
19 def WriteRotateReg32 : SchedWrite;
20 def WriteCLZ : SchedWrite;
21 def WriteCLZ32 : SchedWrite;
22 def WriteCTZ : SchedWrite;
23 def WriteCTZ32 : SchedWrite;
24 def WriteCPOP : SchedWrite;
25 def WriteCPOP32 : SchedWrite;
[all …]
H A DRISCVInstrInfoF.td151 SchedWrite sw>
159 SchedWrite sw>
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZSchedule.td14 def NormalGr : SchedWrite;
15 def Cracked : SchedWrite;
16 def GroupAlone : SchedWrite;
17 def GroupAlone2 : SchedWrite;
18 def GroupAlone3 : SchedWrite;
19 def BeginGroup : SchedWrite;
20 def EndGroup : SchedWrite;
23 def LSULatency : SchedWrite;
39 def "FXa"#Num : SchedWrite;
40 def "FXb"#Num : SchedWrite;
[all …]
H A DSystemZScheduleZ13.td72 def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
96 def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z13_FXaUnit]>;
97 def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z13_FXbUnit]>;
98 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z13_LSUnit]>;
99 def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z13_VecUnit]>;
100 def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z13_VecUnit]>;
101 def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z13_VecUnit]>;
102 def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z13_VecUnit]>;
103 def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z13_VecUnit]>;
104 def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z13_VecUnit]>;
H A DSystemZScheduleZ16.td72 def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
96 def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z16_FXaUnit]>;
97 def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z16_FXbUnit]>;
98 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z16_LSUnit]>;
99 def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z16_VecUnit]>;
100 def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z16_VecUnit]>;
101 def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z16_VecUnit]>;
102 def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z16_VecUnit]>;
103 def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z16_VecUnit]>;
104 def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z16_VecUnit]>;
H A DSystemZScheduleZ15.td72 def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
96 def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z15_FXaUnit]>;
97 def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z15_FXbUnit]>;
98 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z15_LSUnit]>;
99 def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z15_VecUnit]>;
100 def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z15_VecUnit]>;
101 def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z15_VecUnit]>;
102 def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z15_VecUnit]>;
103 def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z15_VecUnit]>;
104 def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z15_VecUnit]>;
H A DSystemZScheduleZ14.td72 def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
96 def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z14_FXaUnit]>;
97 def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z14_FXbUnit]>;
98 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z14_LSUnit]>;
99 def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z14_VecUnit]>;
100 def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z14_VecUnit]>;
101 def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z14_VecUnit]>;
102 def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z14_VecUnit]>;
103 def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z14_VecUnit]>;
104 def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z14_VecUnit]>;
H A DSystemZScheduleZ196.td68 def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
86 def : WriteRes<!cast<SchedWrite>("FXU"#Num), [Z196_FXUnit]>;
87 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z196_LSUnit]>;
88 def : WriteRes<!cast<SchedWrite>("FPU"#Num), [Z196_FPUnit]>;
89 def : WriteRes<!cast<SchedWrite>("DFU"#Num), [Z196_DFUnit]>;
H A DSystemZScheduleZEC12.td68 def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
87 def : WriteRes<!cast<SchedWrite>("FXU"#Num), [ZEC12_FXUnit]>;
88 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [ZEC12_LSUnit]>;
89 def : WriteRes<!cast<SchedWrite>("FPU"#Num), [ZEC12_FPUnit]>;
90 def : WriteRes<!cast<SchedWrite>("DFU"#Num), [ZEC12_DFUnit]>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td20 def WriteImm : SchedWrite; // MOVN, MOVZ
24 def WriteI : SchedWrite; // ALU
32 def WriteIS : SchedWrite; // Shift/Scale
33 def WriteID32 : SchedWrite; // 32-bit Divide
34 def WriteID64 : SchedWrite; // 64-bit Divide
36 def WriteIM32 : SchedWrite; // 32-bit Multiply
40 def WriteBr : SchedWrite; // Branch
63 def WriteLDHi : SchedWrite;
69 def WriteBarrier : SchedWrite; // Memory barrier.
82 def WriteVLD : SchedWrite; // Vector loads.
[all …]
H A DAArch64SchedThunderX.td46 // Subtarget-specific SchedWrite types mapping the ProcResources and
H A DAArch64SchedA53.td52 // Subtarget-specific SchedWrite types which both map the ProcResources and
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86Schedule.td28 def WriteRMW : SchedWrite;
47 SchedWrite Folded;
56 def Ld : SchedWrite;
102 SchedWrite RR = MoveRR;
103 SchedWrite RM = LoadRM;
104 SchedWrite MR = StoreMR;
108 class X86SchedWriteMaskMove<SchedWrite LoadRM, SchedWrite StoreMR> {
109 SchedWrite RM = LoadRM;
110 SchedWrite MR = StoreMR;
212 def WriteZero : SchedWrite;
[all …]
H A DX86ScheduleZnver3.td401 multiclass __zn3WriteRes<SchedWrite SchedRW, list<ProcResourceKind> ExePorts,
429 multiclass Zn3WriteResInt<SchedWrite SchedRW,
435 multiclass Zn3WriteResXMM<SchedWrite SchedRW,
441 multiclass Zn3WriteResYMM<SchedWrite SchedRW,
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMSchedule.td60 def WriteALU : SchedWrite;
70 def WriteCMP : SchedWrite;
89 def WriteDIV : SchedWrite;
92 def WriteLd : SchedWrite;
94 def WriteST : SchedWrite;
97 def WriteBr : SchedWrite;
98 def WriteBrL : SchedWrite;
102 def WriteNoop : SchedWrite;
134 def WriteVLD1 : SchedWrite;
135 def WriteVLD2 : SchedWrite;
[all …]
H A DARMScheduleM4.td37 class M4UnitL1<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 1; }
38 class M4UnitL2<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 2; }
39 class M4UnitL3<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 3; }
40 class M4UnitL14<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 14; }
H A DARMScheduleA9.td2086 [A9WriteLMLo, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
2088 [A9WriteLMHi, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
2151 [A9WriteIssue, !cast<SchedWrite>("A9WriteLfp"#NumAddr#Seq)]>;
2156 [A9WriteF, !cast<SchedWrite>("A9WriteLfp"#NumAddr#Seq)]>;
2186 [A9WriteLMfpLo, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
2191 [A9WriteLMHi, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSISchedule.td19 def WriteBranch : SchedWrite;
20 def WriteExport : SchedWrite;
21 def WriteLDS : SchedWrite;
22 def WriteSALU : SchedWrite;
23 def WriteSMEM : SchedWrite;
24 def WriteVMEM : SchedWrite;
25 def WriteBarrier : SchedWrite;
42 def WriteDouble : SchedWrite;
55 def Write64Bit : SchedWrite;
58 def WriteIntMul : SchedWrite;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiSchedule.td57 def WriteLD : SchedWrite;
58 def WriteST : SchedWrite;
59 def WriteLDSW : SchedWrite;
60 def WriteSTSW : SchedWrite;
61 def WriteALU : SchedWrite;
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSchedule.td219 // single SchedWrite and single SchedRead in any order.
225 class SchedWrite : SchedReadWrite;
226 def NoWrite : SchedWrite;
231 // Define a SchedWrite that is modeled as a sequence of other
241 class WriteSequence<list<SchedWrite> writes, int rep = 1> : SchedWrite {
242 list<SchedWrite> Writes = writes;
272 // SchedWrite is defined by the target, while WriteResources is
273 // defined by the subtarget, and maps the SchedWrite to processor
305 SchedWrite WriteType = write;
319 list<SchedWrite> ValidWrites = writes;
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/llvm-project-15.0.7/llvm/test/TableGen/
H A DCodeGenSchedule-duplicate-instrw.td9 def WriteA : SchedWrite;
10 def WriteB : SchedWrite;
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp108 Record *FindWriteResources(const CodeGenSchedRW &SchedWrite,
864 const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) { in FindWriteResources() argument
868 if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes")) in FindWriteResources()
869 return SchedWrite.TheDef; in FindWriteResources()
872 for (Record *A : SchedWrite.Aliases) { in FindWriteResources()
895 || SchedWrite.TheDef == WR->getValueAsDef("WriteType")) { in FindWriteResources()
909 SchedWrite.TheDef->getName()); in FindWriteResources()
H A DCodeGenSchedule.cpp804 const CodeGenSchedRW &SchedWrite = getSchedRW(RWIdx, IsRead); in expandRWSeqForProc() local
806 for (const Record *Rec : SchedWrite.Aliases) { in expandRWSeqForProc()
824 if (!SchedWrite.IsSequence) { in expandRWSeqForProc()
829 SchedWrite.TheDef ? SchedWrite.TheDef->getValueAsInt("Repeat") : 1; in expandRWSeqForProc()
831 for (unsigned Idx : SchedWrite.Sequence) { in expandRWSeqForProc()

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