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Searched refs:SchedReads (Results 1 – 3 of 3) sorted by relevance

/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenSchedule.h427 std::vector<CodeGenSchedRW> SchedReads; variable
513 assert(Idx < SchedReads.size() && "bad SchedRead index"); in getSchedRead()
514 assert(SchedReads[Idx].isValid() && "invalid SchedRead"); in getSchedRead()
515 return SchedReads[Idx]; in getSchedRead()
H A DCodeGenSchedule.cpp598 SchedReads.resize(1); in collectSchedRW()
675 SchedReads.emplace_back(SchedReads.size(), SRDef); in collectSchedRW()
700 } for (unsigned RIdx = 0, REnd = SchedReads.size(); RIdx != REnd; in collectSchedRW()
703 SchedReads[RIdx].dump(); in collectSchedRW()
730 const std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites; in getSchedRWIdx()
737 for (const CodeGenSchedRW &Read : SchedReads) { in hasReadOfWrite()
840 std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites; in findRWForSequence()
860 std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites; in findOrInsertRW()
935 dbgs() << " " << SchedReads[Read].Name; in collectSchedClasses()
954 dbgs() << " " << SchedReads[RIdx].Name; in collectSchedClasses()
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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleR52.td45 // Cortex-R52 specific SchedReads