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Searched refs:SchedRW (Results 1 – 25 of 60) sorted by relevance

123

/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrTDX.td18 let SchedRW = [WriteSystem], Predicates = [In64BitMode] in {
31 } // SchedRW
34 let SchedRW = [WriteSystem] in {
39 } // SchedRW
H A DX86InstrSystem.td71 } // SchedRW
120 } // SchedRW
139 } // SchedRW
158 } // SchedRW
170 } // SchedRW
181 } // SchedRW
208 } // SchedRW
373 } // SchedRW
421 } // SchedRW
454 } // SchedRW
[all …]
H A DX86InstrFPStack.td330 } // SchedRW
334 } // SchedRW
339 } // SchedRW
347 } // SchedRW
377 } // SchedRW
385 } // SchedRW
402 } // SchedRW
422 } // SchedRW
477 } // SchedRW
516 } // SchedRW
[all …]
H A DX86InstrTSX.td20 let SchedRW = [WriteSystem] in {
49 } // SchedRW
52 let SchedRW = [WriteSystem] in {
61 } // SchedRW
H A DX86InstrShiftRotate.td31 } // Uses = [CL], SchedRW
119 } // SchedRW
219 } // SchedRW
322 } // SchedRW
453 } // SchedRW
553 } // SchedRW
651 } // SchedRW
691 } // SchedRW
736 } // SchedRW
766 } // SchedRW
[all …]
H A DX86InstrKL.td18 let SchedRW = [WriteSystem], Predicates = [HasKL] in {
65 } // SchedRW, Predicates
67 let SchedRW = [WriteSystem], Predicates = [HasWIDEKL] in {
85 } // SchedRW, Predicates
H A DX86InstrInfo.td1305 } // SchedRW
1594 } // SchedRW
1643 } // SchedRW
1659 } // SchedRW
1777 } // SchedRW
1842 } // SchedRW
1875 } // SchedRW
1894 } // SchedRW
1926 } // SchedRW
1946 } // SchedRW
[all …]
H A DX86InstrSGX.td17 let SchedRW = [WriteSystem], Predicates = [HasSGX] in {
29 } // SchedRW
H A DX86InstrSNP.td17 let SchedRW = [WriteSystem] in {
41 } // SchedRW
H A DX86InstrControl.td22 hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
61 let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
73 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump],
109 let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in {
209 let isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
313 isCodeGenOnly = 1, SchedRW = [WriteJump] in
331 let isCall = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in {
400 SchedRW = [WriteJump] in {
420 SchedRW = [WriteJump] in {
437 isCodeGenOnly = 1, SchedRW = [WriteJump] in
H A DX86InstrMMX.td27 isPseudo = 1, SchedRW = [WriteZero], Predicates = [HasMMX] in {
151 let SchedRW = [WriteEMMS],
200 let SchedRW = [WriteVecMove], hasSideEffects = 0, isMoveReg = 1 in {
207 } // SchedRW, hasSideEffects, isMoveReg
219 let SchedRW = [SchedWriteVecMoveLS.MMX.RM] in {
224 } // SchedRW
226 let SchedRW = [SchedWriteVecMoveLS.MMX.MR] in
236 let SchedRW = [SchedWriteVecMoveLS.XMM.RR] in {
256 } // SchedRW
553 let SchedRW = [SchedWriteShuffle.MMX] in {
H A DX86InstrAMX.td18 let SchedRW = [WriteSystem] in {
85 } // SchedRW
89 let SchedRW = [WriteSystem] in {
161 let SchedRW = [WriteSystem] in {
H A DX86InstrSVM.td17 let SchedRW = [WriteSystem] in {
62 } // SchedRW
H A DX86InstrCMovSetCC.td18 isCommutable = 1, SchedRW = [WriteCMOV] in {
39 SchedRW = [WriteCMOV.Folded, WriteCMOV.ReadAfterFold] in {
125 let Uses = [EFLAGS], Defs = [AL], SchedRW = [WriteALU] in {
H A DX86InstrVMX.td17 let SchedRW = [WriteSystem] in {
87 } // SchedRW
H A DX86InstrCompiler.td30 SchedRW = [WriteJump] in
69 let SchedRW = [WriteSystem] in {
162 } // SchedRW
179 let SchedRW = [WriteSystem] in {
233 } // SchedRW
307 let SchedRW = [WriteALU] in {
316 } // SchedRW
324 SchedRW = [WriteALU] in {
446 } // SchedRW
525 } // SchedRW
[all …]
H A DX86ScheduleZnver3.td403 def : WriteRes<SchedRW, ExePorts> {
410 multiclass __zn3WriteResPair<X86FoldableSchedWrite SchedRW,
414 defm : __zn3WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
416 defm : __zn3WriteRes<SchedRW.Folded,
429 multiclass Zn3WriteResInt<SchedWrite SchedRW,
432 defm : __zn3WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
435 multiclass Zn3WriteResXMM<SchedWrite SchedRW,
438 defm : __zn3WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
441 multiclass Zn3WriteResYMM<SchedWrite SchedRW,
444 defm : __zn3WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
[all …]
H A DX86InstrArithmetic.td16 let SchedRW = [WriteLEA] in {
38 } // SchedRW
369 } // Constraints = "$src1 = $dst", SchedRW
372 let SchedRW = [WriteALURMW] in {
389 } // SchedRW
409 let SchedRW = [WriteALURMW] in {
424 } // SchedRW
485 } // CodeSize = 2, SchedRW
533 } // CodeSize = 2, SchedRW
1552 } // SchedRW
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DVOP1Instructions.td85 let SchedRW = ps.SchedRW;
235 let SchedRW = [WriteDoubleCvt] in {
252 } // End SchedRW = [WriteDoubleCvt]
254 let SchedRW = [WriteFloatCvt] in {
277 } // End SchedRW = [WriteFloatCvt]
318 let SchedRW = [WriteDoubleAdd] in {
324 } // End SchedRW = [WriteDoubleAdd]
404 let SchedRW = [WriteTrans64] in {
518 SchedRW = [WriteFloatCvt] in {
601 let SchedRW = ps.SchedRW;
[all …]
H A DVOP3Instructions.td140 let SchedRW = [WriteDoubleAdd] in {
148 } // End SchedRW = [WriteDoubleAdd]
150 let SchedRW = [WriteIntMul] in {
155 } // End SchedRW = [WriteIntMul]
164 let SchedRW = [WriteFloatFMA] in
241 let SchedRW = [WriteDouble] in {
243 } // End SchedRW = [WriteDouble]
245 let SchedRW = [Write64Bit] in {
257 } // End SchedRW = [Write64Bit]
270 let SchedRW = [Write32Bit] in {
[all …]
H A DVOPCInstructions.td153 let SchedRW = ps.SchedRW;
259 let SchedRW = P.Schedule;
270 let SchedRW = P.Schedule;
278 let SchedRW = P.Schedule;
766 let SchedRW = p.Schedule;
773 let SchedRW = p.Schedule;
780 let SchedRW = p.Schedule;
1069 let SchedRW = ps.SchedRW;
1084 let SchedRW = ps.SchedRW;
1119 let SchedRW = ps.SchedRW;
[all …]
H A DVOPDInstructions.td81 let SchedRW = !listconcat(VDX.SchedRW, VDY.SchedRW);
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenSchedule.cpp785 if (!SchedRW.IsSequence) { in expandRWSequence()
790 SchedRW.TheDef ? SchedRW.TheDef->getValueAsInt("Repeat") : 1; in expandRWSequence()
792 for (unsigned I : SchedRW.Sequence) { in expandRWSequence()
863 RWVec.push_back(SchedRW); in findOrInsertRW()
1438 if (SchedRW.HasVariants) { in getIntersectingVariants()
1453 for (RecIter AI = SchedRW.Aliases.begin(), AE = SchedRW.Aliases.end(); in getIntersectingVariants()
1541 if (SchedRW.IsVariadic) { in pushVariant()
2063 if (SchedRW.TheDef) { in collectRWResources()
2066 addWriteRes(SchedRW.TheDef, Idx); in collectRWResources()
2070 addReadAdvance(SchedRW.TheDef, Idx); in collectRWResources()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZfh.td99 let SchedRW = [WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16] in {
111 let SchedRW = [WriteFALU16, ReadFALU16, ReadFALU16] in {
115 let SchedRW = [WriteFMul16, ReadFMul16, ReadFMul16] in
118 let SchedRW = [WriteFDiv16, ReadFDiv16, ReadFDiv16] in
130 let SchedRW = [WriteFSGNJ16, ReadFSGNJ16, ReadFSGNJ16],
137 let SchedRW = [WriteFMinMax16, ReadFMinMax16, ReadFMinMax16] in {
175 let SchedRW = [WriteFCmp16, ReadFCmp16, ReadFCmp16] in {
H A DRISCVInstrInfoD.td104 let SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64] in {
116 let SchedRW = [WriteFALU64, ReadFALU64, ReadFALU64] in {
120 let SchedRW = [WriteFMul64, ReadFMul64, ReadFMul64] in
123 let SchedRW = [WriteFDiv64, ReadFDiv64, ReadFDiv64] in
135 let SchedRW = [WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64],
142 let SchedRW = [WriteFMinMax64, ReadFMinMax64, ReadFMinMax64] in {
154 let SchedRW = [WriteFCmp64, ReadFCmp64, ReadFCmp64] in {

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